board-sh7785lcr.c (464c9e10376b24f04402fa8ef72b66257561bffa) board-sh7785lcr.c (63d12e23235d982d8f55696e09b2ff91e3ba0042)
1/*
2 * Renesas Technology Corp. R0P7785LC0011RL Support.
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive

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19#include <linux/i2c-pca-platform.h>
20#include <linux/i2c-algo-pca.h>
21#include <linux/irq.h>
22#include <linux/clk.h>
23#include <linux/errno.h>
24#include <mach/sh7785lcr.h>
25#include <asm/heartbeat.h>
26#include <asm/clock.h>
1/*
2 * Renesas Technology Corp. R0P7785LC0011RL Support.
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive

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19#include <linux/i2c-pca-platform.h>
20#include <linux/i2c-algo-pca.h>
21#include <linux/irq.h>
22#include <linux/clk.h>
23#include <linux/errno.h>
24#include <mach/sh7785lcr.h>
25#include <asm/heartbeat.h>
26#include <asm/clock.h>
27#include <cpu/sh7785.h>
27
28/*
29 * NOTE: This board has 2 physical memory maps.
30 * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
31 */
32static struct resource heartbeat_resources[] = {
33 [0] = {
34 .start = PLD_LEDCR,

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315
316 pm_power_off = sh7785lcr_power_off;
317
318 /* sm501 DRAM configuration */
319 sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
320 writel(0x000307c2, sm501_reg);
321}
322
28
29/*
30 * NOTE: This board has 2 physical memory maps.
31 * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
32 */
33static struct resource heartbeat_resources[] = {
34 [0] = {
35 .start = PLD_LEDCR,

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316
317 pm_power_off = sh7785lcr_power_off;
318
319 /* sm501 DRAM configuration */
320 sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
321 writel(0x000307c2, sm501_reg);
322}
323
324/* Return the board specific boot mode pin configuration */
325static int sh7785lcr_mode_pins(void)
326{
327 int value = 0;
328
329 /* These are the factory default settings of S1 and S2.
330 * If you change these dip switches then you will need to
331 * adjust the values below as well.
332 */
333 value |= 1 << MODE_PIN_MODE4; /* Clock Mode 16 */
334 value |= 1 << MODE_PIN_MODE5; /* 32-bit Area0 bus width */
335 value |= 1 << MODE_PIN_MODE6; /* 32-bit Area0 bus width */
336 value |= 1 << MODE_PIN_MODE7; /* Area 0 SRAM interface [fixed] */
337 value |= 1 << MODE_PIN_MODE8; /* Little Endian */
338 value |= 1 << MODE_PIN_MODE9; /* Master Mode */
339 value |= 1 << MODE_PIN_MODE14; /* No PLL step-up */
340
341 return value;
342}
343
323/*
324 * The Machine Vector
325 */
326static struct sh_machine_vector mv_sh7785lcr __initmv = {
327 .mv_name = "SH7785LCR",
328 .mv_setup = sh7785lcr_setup,
329 .mv_clk_init = sh7785lcr_clk_init,
330 .mv_init_irq = init_sh7785lcr_IRQ,
344/*
345 * The Machine Vector
346 */
347static struct sh_machine_vector mv_sh7785lcr __initmv = {
348 .mv_name = "SH7785LCR",
349 .mv_setup = sh7785lcr_setup,
350 .mv_clk_init = sh7785lcr_clk_init,
351 .mv_init_irq = init_sh7785lcr_IRQ,
352 .mv_mode_pins = sh7785lcr_mode_pins,
331};
332
353};
354