ipic.c (31d44b57c508971c083ce038d7c5ededd09cea01) ipic.c (476eb4912601a8c01e6702b9a029f476b4b131d2)
1/*
2 * arch/powerpc/sysdev/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 507 unchanged lines hidden (view full) ---

516 out_be32(base + (reg >> 2), value);
517}
518
519static inline struct ipic * ipic_from_irq(unsigned int virq)
520{
521 return primary_ipic;
522}
523
1/*
2 * arch/powerpc/sysdev/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 507 unchanged lines hidden (view full) ---

516 out_be32(base + (reg >> 2), value);
517}
518
519static inline struct ipic * ipic_from_irq(unsigned int virq)
520{
521 return primary_ipic;
522}
523
524#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
525
526static void ipic_unmask_irq(struct irq_data *d)
527{
528 struct ipic *ipic = ipic_from_irq(d->irq);
524static void ipic_unmask_irq(struct irq_data *d)
525{
526 struct ipic *ipic = ipic_from_irq(d->irq);
529 unsigned int src = ipic_irq_to_hw(d->irq);
527 unsigned int src = irqd_to_hwirq(d);
530 unsigned long flags;
531 u32 temp;
532
533 raw_spin_lock_irqsave(&ipic_lock, flags);
534
535 temp = ipic_read(ipic->regs, ipic_info[src].mask);
536 temp |= (1 << (31 - ipic_info[src].bit));
537 ipic_write(ipic->regs, ipic_info[src].mask, temp);
538
539 raw_spin_unlock_irqrestore(&ipic_lock, flags);
540}
541
542static void ipic_mask_irq(struct irq_data *d)
543{
544 struct ipic *ipic = ipic_from_irq(d->irq);
528 unsigned long flags;
529 u32 temp;
530
531 raw_spin_lock_irqsave(&ipic_lock, flags);
532
533 temp = ipic_read(ipic->regs, ipic_info[src].mask);
534 temp |= (1 << (31 - ipic_info[src].bit));
535 ipic_write(ipic->regs, ipic_info[src].mask, temp);
536
537 raw_spin_unlock_irqrestore(&ipic_lock, flags);
538}
539
540static void ipic_mask_irq(struct irq_data *d)
541{
542 struct ipic *ipic = ipic_from_irq(d->irq);
545 unsigned int src = ipic_irq_to_hw(d->irq);
543 unsigned int src = irqd_to_hwirq(d);
546 unsigned long flags;
547 u32 temp;
548
549 raw_spin_lock_irqsave(&ipic_lock, flags);
550
551 temp = ipic_read(ipic->regs, ipic_info[src].mask);
552 temp &= ~(1 << (31 - ipic_info[src].bit));
553 ipic_write(ipic->regs, ipic_info[src].mask, temp);
554
555 /* mb() can't guarantee that masking is finished. But it does finish
556 * for nearly all cases. */
557 mb();
558
559 raw_spin_unlock_irqrestore(&ipic_lock, flags);
560}
561
562static void ipic_ack_irq(struct irq_data *d)
563{
564 struct ipic *ipic = ipic_from_irq(d->irq);
544 unsigned long flags;
545 u32 temp;
546
547 raw_spin_lock_irqsave(&ipic_lock, flags);
548
549 temp = ipic_read(ipic->regs, ipic_info[src].mask);
550 temp &= ~(1 << (31 - ipic_info[src].bit));
551 ipic_write(ipic->regs, ipic_info[src].mask, temp);
552
553 /* mb() can't guarantee that masking is finished. But it does finish
554 * for nearly all cases. */
555 mb();
556
557 raw_spin_unlock_irqrestore(&ipic_lock, flags);
558}
559
560static void ipic_ack_irq(struct irq_data *d)
561{
562 struct ipic *ipic = ipic_from_irq(d->irq);
565 unsigned int src = ipic_irq_to_hw(d->irq);
563 unsigned int src = irqd_to_hwirq(d);
566 unsigned long flags;
567 u32 temp;
568
569 raw_spin_lock_irqsave(&ipic_lock, flags);
570
571 temp = 1 << (31 - ipic_info[src].bit);
572 ipic_write(ipic->regs, ipic_info[src].ack, temp);
573
574 /* mb() can't guarantee that ack is finished. But it does finish
575 * for nearly all cases. */
576 mb();
577
578 raw_spin_unlock_irqrestore(&ipic_lock, flags);
579}
580
581static void ipic_mask_irq_and_ack(struct irq_data *d)
582{
583 struct ipic *ipic = ipic_from_irq(d->irq);
564 unsigned long flags;
565 u32 temp;
566
567 raw_spin_lock_irqsave(&ipic_lock, flags);
568
569 temp = 1 << (31 - ipic_info[src].bit);
570 ipic_write(ipic->regs, ipic_info[src].ack, temp);
571
572 /* mb() can't guarantee that ack is finished. But it does finish
573 * for nearly all cases. */
574 mb();
575
576 raw_spin_unlock_irqrestore(&ipic_lock, flags);
577}
578
579static void ipic_mask_irq_and_ack(struct irq_data *d)
580{
581 struct ipic *ipic = ipic_from_irq(d->irq);
584 unsigned int src = ipic_irq_to_hw(d->irq);
582 unsigned int src = irqd_to_hwirq(d);
585 unsigned long flags;
586 u32 temp;
587
588 raw_spin_lock_irqsave(&ipic_lock, flags);
589
590 temp = ipic_read(ipic->regs, ipic_info[src].mask);
591 temp &= ~(1 << (31 - ipic_info[src].bit));
592 ipic_write(ipic->regs, ipic_info[src].mask, temp);

--- 6 unchanged lines hidden (view full) ---

599 mb();
600
601 raw_spin_unlock_irqrestore(&ipic_lock, flags);
602}
603
604static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
605{
606 struct ipic *ipic = ipic_from_irq(d->irq);
583 unsigned long flags;
584 u32 temp;
585
586 raw_spin_lock_irqsave(&ipic_lock, flags);
587
588 temp = ipic_read(ipic->regs, ipic_info[src].mask);
589 temp &= ~(1 << (31 - ipic_info[src].bit));
590 ipic_write(ipic->regs, ipic_info[src].mask, temp);

--- 6 unchanged lines hidden (view full) ---

597 mb();
598
599 raw_spin_unlock_irqrestore(&ipic_lock, flags);
600}
601
602static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
603{
604 struct ipic *ipic = ipic_from_irq(d->irq);
607 unsigned int src = ipic_irq_to_hw(d->irq);
605 unsigned int src = irqd_to_hwirq(d);
608 unsigned int vold, vnew, edibit;
609
610 if (flow_type == IRQ_TYPE_NONE)
611 flow_type = IRQ_TYPE_LEVEL_LOW;
612
613 /* ipic supports only low assertion and high-to-low change senses
614 */
615 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {

--- 172 unchanged lines hidden (view full) ---

788 primary_ipic->regs);
789
790 return ipic;
791}
792
793int ipic_set_priority(unsigned int virq, unsigned int priority)
794{
795 struct ipic *ipic = ipic_from_irq(virq);
606 unsigned int vold, vnew, edibit;
607
608 if (flow_type == IRQ_TYPE_NONE)
609 flow_type = IRQ_TYPE_LEVEL_LOW;
610
611 /* ipic supports only low assertion and high-to-low change senses
612 */
613 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {

--- 172 unchanged lines hidden (view full) ---

786 primary_ipic->regs);
787
788 return ipic;
789}
790
791int ipic_set_priority(unsigned int virq, unsigned int priority)
792{
793 struct ipic *ipic = ipic_from_irq(virq);
796 unsigned int src = ipic_irq_to_hw(virq);
794 unsigned int src = virq_to_hw(virq);
797 u32 temp;
798
799 if (priority > 7)
800 return -EINVAL;
801 if (src > 127)
802 return -EINVAL;
803 if (ipic_info[src].prio == 0)
804 return -EINVAL;

--- 11 unchanged lines hidden (view full) ---

816 ipic_write(ipic->regs, ipic_info[src].prio, temp);
817
818 return 0;
819}
820
821void ipic_set_highest_priority(unsigned int virq)
822{
823 struct ipic *ipic = ipic_from_irq(virq);
795 u32 temp;
796
797 if (priority > 7)
798 return -EINVAL;
799 if (src > 127)
800 return -EINVAL;
801 if (ipic_info[src].prio == 0)
802 return -EINVAL;

--- 11 unchanged lines hidden (view full) ---

814 ipic_write(ipic->regs, ipic_info[src].prio, temp);
815
816 return 0;
817}
818
819void ipic_set_highest_priority(unsigned int virq)
820{
821 struct ipic *ipic = ipic_from_irq(virq);
824 unsigned int src = ipic_irq_to_hw(virq);
822 unsigned int src = virq_to_hw(virq);
825 u32 temp;
826
827 temp = ipic_read(ipic->regs, IPIC_SICFR);
828
829 /* clear and set HPI */
830 temp &= 0x7f000000;
831 temp |= (src & 0x7f) << 24;
832

--- 160 unchanged lines hidden --- 		823 u32 temp;
824
825 temp = ipic_read(ipic->regs, IPIC_SICFR);
826
827 /* clear and set HPI */
828 temp &= 0x7f000000;
829 temp |= (src & 0x7f) << 24;
830

--- 160 unchanged lines hidden ---