setup.c (6ea24cf79e055f0a62a64baa8587e2254a493c7b) setup.c (8cc7581cdb84a232468c41bc417183a423dfbb07)
1/*
2 * 64-bit pSeries and RS/6000 setup code.
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * Modified by PPC64 Team, IBM Corp
8 *

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52#include <asm/pci-bridge.h>
53#include <asm/iommu.h>
54#include <asm/dma.h>
55#include <asm/machdep.h>
56#include <asm/irq.h>
57#include <asm/time.h>
58#include <asm/nvram.h>
59#include <asm/pmc.h>
1/*
2 * 64-bit pSeries and RS/6000 setup code.
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * Modified by PPC64 Team, IBM Corp
8 *

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52#include <asm/pci-bridge.h>
53#include <asm/iommu.h>
54#include <asm/dma.h>
55#include <asm/machdep.h>
56#include <asm/irq.h>
57#include <asm/time.h>
58#include <asm/nvram.h>
59#include <asm/pmc.h>
60#include <asm/mpic.h>
61#include <asm/xics.h>
62#include <asm/ppc-pci.h>
63#include <asm/i8259.h>
64#include <asm/udbg.h>
65#include <asm/smp.h>
66#include <asm/firmware.h>
67#include <asm/eeh.h>
68#include <asm/reg.h>
69#include <asm/plpar_wrappers.h>
70
71#include "pseries.h"
72
73int CMO_PrPSP = -1;
74int CMO_SecPSP = -1;
75unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K);
76EXPORT_SYMBOL(CMO_PageSize);
77
78int fwnmi_active; /* TRUE if an FWNMI handler is present */
79
60#include <asm/xics.h>
61#include <asm/ppc-pci.h>
62#include <asm/i8259.h>
63#include <asm/udbg.h>
64#include <asm/smp.h>
65#include <asm/firmware.h>
66#include <asm/eeh.h>
67#include <asm/reg.h>
68#include <asm/plpar_wrappers.h>
69
70#include "pseries.h"
71
72int CMO_PrPSP = -1;
73int CMO_SecPSP = -1;
74unsigned long CMO_PageSize = (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K);
75EXPORT_SYMBOL(CMO_PageSize);
76
77int fwnmi_active; /* TRUE if an FWNMI handler is present */
78
80static struct device_node *pSeries_mpic_node;
81
82static void pSeries_show_cpuinfo(struct seq_file *m)
83{
84 struct device_node *root;
85 const char *model = "";
86
87 root = of_find_node_by_path("/");
88 if (root)
89 model = of_get_property(root, "model", NULL);

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167 }
168 if (intack)
169 printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
170 i8259_init(found, intack);
171 of_node_put(found);
172 irq_set_chained_handler(cascade, pseries_8259_cascade);
173}
174
79static void pSeries_show_cpuinfo(struct seq_file *m)
80{
81 struct device_node *root;
82 const char *model = "";
83
84 root = of_find_node_by_path("/");
85 if (root)
86 model = of_get_property(root, "model", NULL);

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164 }
165 if (intack)
166 printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
167 i8259_init(found, intack);
168 of_node_put(found);
169 irq_set_chained_handler(cascade, pseries_8259_cascade);
170}
171
175static void __init pseries_mpic_init_IRQ(void)
172static void __init pseries_init_irq(void)
176{
173{
177 struct device_node *np;
178 const unsigned int *opprop;
179 unsigned long openpic_addr = 0;
180 int naddr, n, i, opplen;
181 struct mpic *mpic;
182
183 np = of_find_node_by_path("/");
184 naddr = of_n_addr_cells(np);
185 opprop = of_get_property(np, "platform-open-pic", &opplen);
186 if (opprop != NULL) {
187 openpic_addr = of_read_number(opprop, naddr);
188 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
189 }
190 of_node_put(np);
191
192 BUG_ON(openpic_addr == 0);
193
194 /* Setup the openpic driver */
195 mpic = mpic_alloc(pSeries_mpic_node, openpic_addr,
196 MPIC_NO_RESET, 16, 0, " MPIC ");
197 BUG_ON(mpic == NULL);
198
199 /* Add ISUs */
200 opplen /= sizeof(u32);
201 for (n = 0, i = naddr; i < opplen; i += naddr, n++) {
202 unsigned long isuaddr = of_read_number(opprop + i, naddr);
203 mpic_assign_isu(mpic, n, isuaddr);
204 }
205
206 /* Setup top-level get_irq */
207 ppc_md.get_irq = mpic_get_irq;
208
209 /* All ISUs are setup, complete initialization */
210 mpic_init(mpic);
211
212 /* Look for cascade */
213 pseries_setup_i8259_cascade();
214}
215
216static void __init pseries_xics_init_IRQ(void)
217{
218 xics_init();
219 pseries_setup_i8259_cascade();
220}
221
222static void pseries_lpar_enable_pmcs(void)
223{
224 unsigned long set, reset;
225
226 set = 1UL << 63;
227 reset = 0;
228 plpar_hcall_norets(H_PERFMON, set, reset);
229}
230
174 xics_init();
175 pseries_setup_i8259_cascade();
176}
177
178static void pseries_lpar_enable_pmcs(void)
179{
180 unsigned long set, reset;
181
182 set = 1UL << 63;
183 reset = 0;
184 plpar_hcall_norets(H_PERFMON, set, reset);
185}
186
231static void __init pseries_discover_pic(void)
232{
233 struct device_node *np;
234 const char *typep;
235
236 for_each_node_by_name(np, "interrupt-controller") {
237 typep = of_get_property(np, "compatible", NULL);
238 if (strstr(typep, "open-pic")) {
239 pSeries_mpic_node = of_node_get(np);
240 ppc_md.init_IRQ = pseries_mpic_init_IRQ;
241 setup_kexec_cpu_down_mpic();
242 smp_init_pseries_mpic();
243 return;
244 } else if (strstr(typep, "ppc-xicp")) {
245 ppc_md.init_IRQ = pseries_xics_init_IRQ;
246 setup_kexec_cpu_down_xics();
247 smp_init_pseries_xics();
248 return;
249 }
250 }
251 printk(KERN_ERR "pSeries_discover_pic: failed to recognize"
252 " interrupt-controller\n");
253}
254
255static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
256{
257 struct of_reconfig_data *rd = data;
258 struct device_node *parent, *np = rd->dn;
259 struct pci_dn *pdn;
260 int err = NOTIFY_OK;
261
262 switch (action) {
263 case OF_RECONFIG_ATTACH_NODE:
264 parent = of_get_parent(np);
265 pdn = parent ? PCI_DN(parent) : NULL;
187static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data)
188{
189 struct of_reconfig_data *rd = data;
190 struct device_node *parent, *np = rd->dn;
191 struct pci_dn *pdn;
192 int err = NOTIFY_OK;
193
194 switch (action) {
195 case OF_RECONFIG_ATTACH_NODE:
196 parent = of_get_parent(np);
197 pdn = parent ? PCI_DN(parent) : NULL;
266 if (pdn) {
267 /* Create pdn and EEH device */
268 update_dn_pci_info(np, pdn->phb);
269 eeh_dev_init(PCI_DN(np), pdn->phb);
270 }
198 if (pdn)
199 pci_add_device_node_info(pdn->phb, np);
271
272 of_node_put(parent);
273 break;
274 case OF_RECONFIG_DETACH_NODE:
275 pdn = PCI_DN(np);
276 if (pdn)
277 list_del(&pdn->list);
278 break;

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360 return alloc_dispatch_logs();
361}
362machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache);
363
364static void pseries_lpar_idle(void)
365{
366 /*
367 * Default handler to go into low thread priority and possibly
200
201 of_node_put(parent);
202 break;
203 case OF_RECONFIG_DETACH_NODE:
204 pdn = PCI_DN(np);
205 if (pdn)
206 list_del(&pdn->list);
207 break;

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289 return alloc_dispatch_logs();
290}
291machine_early_initcall(pseries, alloc_dispatch_log_kmem_cache);
292
293static void pseries_lpar_idle(void)
294{
295 /*
296 * Default handler to go into low thread priority and possibly
368 * low power mode by cedeing processor to hypervisor
297 * low power mode by ceding processor to hypervisor
369 */
370
371 /* Indicate to hypervisor that we are idle. */
372 get_lppaca()->idle = 1;
373
374 /*
375 * Yield the processor to the hypervisor. We return if
376 * an external interrupt occurs (which are driven prior

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485 continue;
486 rtas_setup_phb(phb);
487 pci_process_bridge_OF_ranges(phb, node, 0);
488 isa_bridge_find_early(phb);
489 phb->controller_ops = pseries_pci_controller_ops;
490 }
491
492 of_node_put(root);
298 */
299
300 /* Indicate to hypervisor that we are idle. */
301 get_lppaca()->idle = 1;
302
303 /*
304 * Yield the processor to the hypervisor. We return if
305 * an external interrupt occurs (which are driven prior

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414 continue;
415 rtas_setup_phb(phb);
416 pci_process_bridge_OF_ranges(phb, node, 0);
417 isa_bridge_find_early(phb);
418 phb->controller_ops = pseries_pci_controller_ops;
419 }
420
421 of_node_put(root);
493 pci_devs_phb_init();
494
495 /*
496 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
497 * in chosen.
498 */
499 of_pci_check_probe_only();
500}
501
502static void __init pSeries_setup_arch(void)
503{
504 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
505
506 /* Discover PIC type and setup ppc_md accordingly */
422
423 /*
424 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
425 * in chosen.
426 */
427 of_pci_check_probe_only();
428}
429
430static void __init pSeries_setup_arch(void)
431{
432 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
433
434 /* Discover PIC type and setup ppc_md accordingly */
507 pseries_discover_pic();
435 smp_init_pseries();
508
436
437
509 /* openpic global configuration register (64-bit format). */
510 /* openpic Interrupt Source Unit pointer (64-bit format). */
511 /* python0 facility area (mmio) (64-bit format) REAL address. */
512
513 /* init to some ~sane value until calibrate_delay() runs */
514 loops_per_jiffy = 50000000;
515
516 fwnmi_init();

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831 .probe_mode = pSeries_pci_probe_mode,
832};
833
834define_machine(pseries) {
835 .name = "pSeries",
836 .probe = pSeries_probe,
837 .setup_arch = pSeries_setup_arch,
838 .init_early = pSeries_init_early,
438 /* openpic global configuration register (64-bit format). */
439 /* openpic Interrupt Source Unit pointer (64-bit format). */
440 /* python0 facility area (mmio) (64-bit format) REAL address. */
441
442 /* init to some ~sane value until calibrate_delay() runs */
443 loops_per_jiffy = 50000000;
444
445 fwnmi_init();

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760 .probe_mode = pSeries_pci_probe_mode,
761};
762
763define_machine(pseries) {
764 .name = "pSeries",
765 .probe = pSeries_probe,
766 .setup_arch = pSeries_setup_arch,
767 .init_early = pSeries_init_early,
768 .init_IRQ = pseries_init_irq,
839 .show_cpuinfo = pSeries_show_cpuinfo,
840 .log_error = pSeries_log_error,
841 .pcibios_fixup = pSeries_final_fixup,
842 .restart = rtas_restart,
843 .halt = rtas_halt,
844 .panic = rtas_os_term,
845 .get_boot_time = rtas_get_boot_time,
846 .get_rtc_time = rtas_get_rtc_time,
847 .set_rtc_time = rtas_set_rtc_time,
848 .calibrate_decr = generic_calibrate_decr,
849 .progress = rtas_progress,
850 .system_reset_exception = pSeries_system_reset_exception,
851 .machine_check_exception = pSeries_machine_check_exception,
852#ifdef CONFIG_KEXEC
853 .machine_kexec = pSeries_machine_kexec,
769 .show_cpuinfo = pSeries_show_cpuinfo,
770 .log_error = pSeries_log_error,
771 .pcibios_fixup = pSeries_final_fixup,
772 .restart = rtas_restart,
773 .halt = rtas_halt,
774 .panic = rtas_os_term,
775 .get_boot_time = rtas_get_boot_time,
776 .get_rtc_time = rtas_get_rtc_time,
777 .set_rtc_time = rtas_set_rtc_time,
778 .calibrate_decr = generic_calibrate_decr,
779 .progress = rtas_progress,
780 .system_reset_exception = pSeries_system_reset_exception,
781 .machine_check_exception = pSeries_machine_check_exception,
782#ifdef CONFIG_KEXEC
783 .machine_kexec = pSeries_machine_kexec,
784 .kexec_cpu_down = pseries_kexec_cpu_down,
854#endif
855#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
856 .memory_block_size = pseries_memory_block_size,
857#endif
858};
785#endif
786#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
787 .memory_block_size = pseries_memory_block_size,
788#endif
789};