sleep.S (f0eef25339f92f7cd4aeea23d9ae97987a5a1e82) sleep.S (7c03d653cd257793dc40520c94e229b5fd0578e7)
1/*
2 * This file contains sleep low-level functions for PowerBook G3.
3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * and Paul Mackerras (paulus@samba.org).
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12
13#include <asm/processor.h>
14#include <asm/page.h>
15#include <asm/ppc_asm.h>
16#include <asm/cputable.h>
17#include <asm/cache.h>
18#include <asm/thread_info.h>
19#include <asm/asm-offsets.h>
1/*
2 * This file contains sleep low-level functions for PowerBook G3.
3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * and Paul Mackerras (paulus@samba.org).
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12
13#include <asm/processor.h>
14#include <asm/page.h>
15#include <asm/ppc_asm.h>
16#include <asm/cputable.h>
17#include <asm/cache.h>
18#include <asm/thread_info.h>
19#include <asm/asm-offsets.h>
20#include <asm/mmu.h>
20
21#define MAGIC 0x4c617273 /* 'Lars' */
22
23/*
24 * Structure for storing CPU registers on the stack.
25 */
26#define SL_SP 0
27#define SL_PC 4

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318 mtibatu 2,r4
319 lwz r4,SL_IBAT2+4(r1)
320 mtibatl 2,r4
321 lwz r4,SL_IBAT3(r1)
322 mtibatu 3,r4
323 lwz r4,SL_IBAT3+4(r1)
324 mtibatl 3,r4
325
21
22#define MAGIC 0x4c617273 /* 'Lars' */
23
24/*
25 * Structure for storing CPU registers on the stack.
26 */
27#define SL_SP 0
28#define SL_PC 4

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319 mtibatu 2,r4
320 lwz r4,SL_IBAT2+4(r1)
321 mtibatl 2,r4
322 lwz r4,SL_IBAT3(r1)
323 mtibatu 3,r4
324 lwz r4,SL_IBAT3+4(r1)
325 mtibatl 3,r4
326
326BEGIN_FTR_SECTION
327BEGIN_MMU_FTR_SECTION
327 li r4,0
328 mtspr SPRN_DBAT4U,r4
329 mtspr SPRN_DBAT4L,r4
330 mtspr SPRN_DBAT5U,r4
331 mtspr SPRN_DBAT5L,r4
332 mtspr SPRN_DBAT6U,r4
333 mtspr SPRN_DBAT6L,r4
334 mtspr SPRN_DBAT7U,r4
335 mtspr SPRN_DBAT7L,r4
336 mtspr SPRN_IBAT4U,r4
337 mtspr SPRN_IBAT4L,r4
338 mtspr SPRN_IBAT5U,r4
339 mtspr SPRN_IBAT5L,r4
340 mtspr SPRN_IBAT6U,r4
341 mtspr SPRN_IBAT6L,r4
342 mtspr SPRN_IBAT7U,r4
343 mtspr SPRN_IBAT7L,r4
328 li r4,0
329 mtspr SPRN_DBAT4U,r4
330 mtspr SPRN_DBAT4L,r4
331 mtspr SPRN_DBAT5U,r4
332 mtspr SPRN_DBAT5L,r4
333 mtspr SPRN_DBAT6U,r4
334 mtspr SPRN_DBAT6L,r4
335 mtspr SPRN_DBAT7U,r4
336 mtspr SPRN_DBAT7L,r4
337 mtspr SPRN_IBAT4U,r4
338 mtspr SPRN_IBAT4L,r4
339 mtspr SPRN_IBAT5U,r4
340 mtspr SPRN_IBAT5L,r4
341 mtspr SPRN_IBAT6U,r4
342 mtspr SPRN_IBAT6L,r4
343 mtspr SPRN_IBAT7U,r4
344 mtspr SPRN_IBAT7L,r4
344END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
345END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
345
346 /* Flush all TLBs */
347 lis r4,0x1000
3481: addic. r4,r4,-0x1000
349 tlbie r4
350 blt 1b
351 sync
352

--- 44 unchanged lines hidden --- 		346
347 /* Flush all TLBs */
348 lis r4,0x1000
3491: addic. r4,r4,-0x1000
350 tlbie r4
351 blt 1b
352 sync
353

--- 44 unchanged lines hidden ---