pic.c (31d44b57c508971c083ce038d7c5ededd09cea01) pic.c (476eb4912601a8c01e6702b9a029f476b4b131d2)
1/*
2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
5 * in a separate file
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)

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79 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
80 atomic_inc(&ppc_n_lost_interrupts);
81 set_dec(1);
82 }
83}
84
85static void pmac_mask_and_ack_irq(struct irq_data *d)
86{
1/*
2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
5 * in a separate file
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)

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79 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
80 atomic_inc(&ppc_n_lost_interrupts);
81 set_dec(1);
82 }
83}
84
85static void pmac_mask_and_ack_irq(struct irq_data *d)
86{
87 unsigned int src = irq_map[d->irq].hwirq;
87 unsigned int src = irqd_to_hwirq(d);
88 unsigned long bit = 1UL << (src & 0x1f);
89 int i = src >> 5;
90 unsigned long flags;
91
92 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
93 __clear_bit(src, ppc_cached_irq_mask);
94 if (__test_and_clear_bit(src, ppc_lost_interrupts))
95 atomic_dec(&ppc_n_lost_interrupts);

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101 mb();
102 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
103 != (ppc_cached_irq_mask[i] & bit));
104 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
105}
106
107static void pmac_ack_irq(struct irq_data *d)
108{
88 unsigned long bit = 1UL << (src & 0x1f);
89 int i = src >> 5;
90 unsigned long flags;
91
92 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
93 __clear_bit(src, ppc_cached_irq_mask);
94 if (__test_and_clear_bit(src, ppc_lost_interrupts))
95 atomic_dec(&ppc_n_lost_interrupts);

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101 mb();
102 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
103 != (ppc_cached_irq_mask[i] & bit));
104 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
105}
106
107static void pmac_ack_irq(struct irq_data *d)
108{
109 unsigned int src = irq_map[d->irq].hwirq;
109 unsigned int src = irqd_to_hwirq(d);
110 unsigned long bit = 1UL << (src & 0x1f);
111 int i = src >> 5;
112 unsigned long flags;
113
114 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
115 if (__test_and_clear_bit(src, ppc_lost_interrupts))
116 atomic_dec(&ppc_n_lost_interrupts);
117 out_le32(&pmac_irq_hw[i]->ack, bit);

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147}
148
149/* When an irq gets requested for the first client, if it's an
150 * edge interrupt, we clear any previous one on the controller
151 */
152static unsigned int pmac_startup_irq(struct irq_data *d)
153{
154 unsigned long flags;
110 unsigned long bit = 1UL << (src & 0x1f);
111 int i = src >> 5;
112 unsigned long flags;
113
114 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
115 if (__test_and_clear_bit(src, ppc_lost_interrupts))
116 atomic_dec(&ppc_n_lost_interrupts);
117 out_le32(&pmac_irq_hw[i]->ack, bit);

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147}
148
149/* When an irq gets requested for the first client, if it's an
150 * edge interrupt, we clear any previous one on the controller
151 */
152static unsigned int pmac_startup_irq(struct irq_data *d)
153{
154 unsigned long flags;
155 unsigned int src = irq_map[d->irq].hwirq;
155 unsigned int src = irqd_to_hwirq(d);
156 unsigned long bit = 1UL << (src & 0x1f);
157 int i = src >> 5;
158
159 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
160 if (!irqd_is_level_type(d))
161 out_le32(&pmac_irq_hw[i]->ack, bit);
162 __set_bit(src, ppc_cached_irq_mask);
163 __pmac_set_irq_mask(src, 0);
164 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
165
166 return 0;
167}
168
169static void pmac_mask_irq(struct irq_data *d)
170{
171 unsigned long flags;
156 unsigned long bit = 1UL << (src & 0x1f);
157 int i = src >> 5;
158
159 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
160 if (!irqd_is_level_type(d))
161 out_le32(&pmac_irq_hw[i]->ack, bit);
162 __set_bit(src, ppc_cached_irq_mask);
163 __pmac_set_irq_mask(src, 0);
164 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
165
166 return 0;
167}
168
169static void pmac_mask_irq(struct irq_data *d)
170{
171 unsigned long flags;
172 unsigned int src = irq_map[d->irq].hwirq;
172 unsigned int src = irqd_to_hwirq(d);
173
174 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
175 __clear_bit(src, ppc_cached_irq_mask);
176 __pmac_set_irq_mask(src, 1);
177 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
178}
179
180static void pmac_unmask_irq(struct irq_data *d)
181{
182 unsigned long flags;
173
174 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
175 __clear_bit(src, ppc_cached_irq_mask);
176 __pmac_set_irq_mask(src, 1);
177 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
178}
179
180static void pmac_unmask_irq(struct irq_data *d)
181{
182 unsigned long flags;
183 unsigned int src = irq_map[d->irq].hwirq;
183 unsigned int src = irqd_to_hwirq(d);
184
185 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
186 __set_bit(src, ppc_cached_irq_mask);
187 __pmac_set_irq_mask(src, 0);
188 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
189}
190
191static int pmac_retrigger(struct irq_data *d)
192{
193 unsigned long flags;
194
195 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
184
185 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
186 __set_bit(src, ppc_cached_irq_mask);
187 __pmac_set_irq_mask(src, 0);
188 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
189}
190
191static int pmac_retrigger(struct irq_data *d)
192{
193 unsigned long flags;
194
195 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
196 __pmac_retrigger(irq_map[d->irq].hwirq);
196 __pmac_retrigger(irqd_to_hwirq(d));
197 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
198 return 1;
199}
200
201static struct irq_chip pmac_pic = {
202 .name = "PMAC-PIC",
203 .irq_startup = pmac_startup_irq,
204 .irq_mask = pmac_mask_irq,

--- 543 unchanged lines hidden --- 		197 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
198 return 1;
199}
200
201static struct irq_chip pmac_pic = {
202 .name = "PMAC-PIC",
203 .irq_startup = pmac_startup_irq,
204 .irq_mask = pmac_mask_irq,

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