tlb.c (dfc3095cec27f402c183da920f4733785e4c873d) tlb.c (3e7318584dfec11992f3ac45658c4bc1210b3778)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * This file contains the routines for TLB flushing.
4 * On machines where the MMU does not use a hash table to store virtual to
5 * physical translations (ie, SW loaded TLBs or Book3E compilant processors,
6 * this does -not- include 603 however which shares the implementation with
7 * hash based processors)
8 *

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45#include <mm/mmu_decl.h>
46
47/*
48 * This struct lists the sw-supported page sizes. The hardawre MMU may support
49 * other sizes not listed here. The .ind field is only used on MMUs that have
50 * indirect page table entries.
51 */
52#if defined(CONFIG_PPC_BOOK3E_MMU) || defined(CONFIG_PPC_8xx)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * This file contains the routines for TLB flushing.
4 * On machines where the MMU does not use a hash table to store virtual to
5 * physical translations (ie, SW loaded TLBs or Book3E compilant processors,
6 * this does -not- include 603 however which shares the implementation with
7 * hash based processors)
8 *

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45#include <mm/mmu_decl.h>
46
47/*
48 * This struct lists the sw-supported page sizes. The hardawre MMU may support
49 * other sizes not listed here. The .ind field is only used on MMUs that have
50 * indirect page table entries.
51 */
52#if defined(CONFIG_PPC_BOOK3E_MMU) || defined(CONFIG_PPC_8xx)
53#ifdef CONFIG_PPC_FSL_BOOK3E
53#ifdef CONFIG_PPC_E500
54struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
55 [MMU_PAGE_4K] = {
56 .shift = 12,
57 .enc = BOOK3E_PAGESZ_4K,
58 },
59 [MMU_PAGE_2M] = {
60 .shift = 21,
61 .enc = BOOK3E_PAGESZ_2M,

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161 * exceptions. This is used for bolted and e6500 TLB miss handlers which
162 * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
163 * this is set to zero.
164 */
165int extlb_level_exc;
166
167#endif /* CONFIG_PPC64 */
168
54struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
55 [MMU_PAGE_4K] = {
56 .shift = 12,
57 .enc = BOOK3E_PAGESZ_4K,
58 },
59 [MMU_PAGE_2M] = {
60 .shift = 21,
61 .enc = BOOK3E_PAGESZ_2M,

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161 * exceptions. This is used for bolted and e6500 TLB miss handlers which
162 * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
163 * this is set to zero.
164 */
165int extlb_level_exc;
166
167#endif /* CONFIG_PPC64 */
168
169#ifdef CONFIG_PPC_FSL_BOOK3E
169#ifdef CONFIG_PPC_E500
170/* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
171DEFINE_PER_CPU(int, next_tlbcam_idx);
172EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
173#endif
174
175/*
176 * Base TLB flushing operations:
177 *

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436
437static void __init setup_page_sizes(void)
438{
439 unsigned int tlb0cfg;
440 unsigned int tlb0ps;
441 unsigned int eptcfg;
442 int i, psize;
443
170/* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
171DEFINE_PER_CPU(int, next_tlbcam_idx);
172EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
173#endif
174
175/*
176 * Base TLB flushing operations:
177 *

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436
437static void __init setup_page_sizes(void)
438{
439 unsigned int tlb0cfg;
440 unsigned int tlb0ps;
441 unsigned int eptcfg;
442 int i, psize;
443
444#ifdef CONFIG_PPC_FSL_BOOK3E
444#ifdef CONFIG_PPC_E500
445 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
446 int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
447
448 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
449 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
450 unsigned int min_pg, max_pg;
451
452 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;

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579 * handlers to branch to the one dedicated to it.
580 */
581
582 switch (book3e_htw_mode) {
583 case PPC_HTW_IBM:
584 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
585 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
586 break;
445 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
446 int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
447
448 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
449 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
450 unsigned int min_pg, max_pg;
451
452 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;

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579 * handlers to branch to the one dedicated to it.
580 */
581
582 switch (book3e_htw_mode) {
583 case PPC_HTW_IBM:
584 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
585 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
586 break;
587#ifdef CONFIG_PPC_FSL_BOOK3E
587#ifdef CONFIG_PPC_E500
588 case PPC_HTW_E6500:
589 extlb_level_exc = EX_TLB_SIZE;
590 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
591 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
592 break;
593#endif
594 }
595 pr_info("MMU: Book3E HW tablewalk %s\n",

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622
623 case PPC_HTW_NONE:
624 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
625 mmu_pte_psize = mmu_virtual_psize;
626 break;
627 }
628 mtspr(SPRN_MAS4, mas4);
629
588 case PPC_HTW_E6500:
589 extlb_level_exc = EX_TLB_SIZE;
590 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
591 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
592 break;
593#endif
594 }
595 pr_info("MMU: Book3E HW tablewalk %s\n",

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622
623 case PPC_HTW_NONE:
624 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
625 mmu_pte_psize = mmu_virtual_psize;
626 break;
627 }
628 mtspr(SPRN_MAS4, mas4);
629
630#ifdef CONFIG_PPC_FSL_BOOK3E
630#ifdef CONFIG_PPC_E500
631 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
632 unsigned int num_cams;
633 bool map = true;
634
635 /* use a quarter of the TLBCAM for bolted linear map */
636 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
637
638 /*

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675 * the IND entries from the array loaded by the PT.
676 */
677 /* Look for supported page sizes */
678 setup_page_sizes();
679
680 /* Look for HW tablewalk support */
681 setup_mmu_htw();
682
631 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
632 unsigned int num_cams;
633 bool map = true;
634
635 /* use a quarter of the TLBCAM for bolted linear map */
636 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
637
638 /*

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675 * the IND entries from the array loaded by the PT.
676 */
677 /* Look for supported page sizes */
678 setup_page_sizes();
679
680 /* Look for HW tablewalk support */
681 setup_mmu_htw();
682
683#ifdef CONFIG_PPC_FSL_BOOK3E
683#ifdef CONFIG_PPC_E500
684 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
685 if (book3e_htw_mode == PPC_HTW_NONE) {
686 extlb_level_exc = EX_TLB_SIZE;
687 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
688 patch_exception(0x1e0,
689 exc_instruction_tlb_miss_bolted_book3e);
690 }
691 }

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696 */
697 linear_map_top = memblock_end_of_DRAM();
698
699 ioremap_bot = IOREMAP_BASE;
700}
701
702static void __init early_mmu_set_memory_limit(void)
703{
684 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
685 if (book3e_htw_mode == PPC_HTW_NONE) {
686 extlb_level_exc = EX_TLB_SIZE;
687 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
688 patch_exception(0x1e0,
689 exc_instruction_tlb_miss_bolted_book3e);
690 }
691 }

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696 */
697 linear_map_top = memblock_end_of_DRAM();
698
699 ioremap_bot = IOREMAP_BASE;
700}
701
702static void __init early_mmu_set_memory_limit(void)
703{
704#ifdef CONFIG_PPC_FSL_BOOK3E
704#ifdef CONFIG_PPC_E500
705 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
706 /*
707 * Limit memory so we dont have linear faults.
708 * Unlike memblock_set_current_limit, which limits
709 * memory available during early boot, this permanently
710 * reduces the memory available to Linux. We need to
711 * do this because highmem is not supported on 64-bit.
712 */

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745 * mappable if this memblock is the only one. Additional memblocks
746 * can only increase, not decrease, the amount that ends up getting
747 * mapped. We still limit max to 1G even if we'll eventually map
748 * more. This is due to what the early init code is set up to do.
749 *
750 * We crop it to the size of the first MEMBLOCK to
751 * avoid going over total available memory just in case...
752 */
705 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
706 /*
707 * Limit memory so we dont have linear faults.
708 * Unlike memblock_set_current_limit, which limits
709 * memory available during early boot, this permanently
710 * reduces the memory available to Linux. We need to
711 * do this because highmem is not supported on 64-bit.
712 */

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745 * mappable if this memblock is the only one. Additional memblocks
746 * can only increase, not decrease, the amount that ends up getting
747 * mapped. We still limit max to 1G even if we'll eventually map
748 * more. This is due to what the early init code is set up to do.
749 *
750 * We crop it to the size of the first MEMBLOCK to
751 * avoid going over total available memory just in case...
752 */
753#ifdef CONFIG_PPC_FSL_BOOK3E
753#ifdef CONFIG_PPC_E500
754 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
755 unsigned long linear_sz;
756 unsigned int num_cams;
757
758 /* use a quarter of the TLBCAM for bolted linear map */
759 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
760
761 linear_sz = map_mem_in_cams(first_memblock_size, num_cams,

--- 18 unchanged lines hidden --- 		754 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
755 unsigned long linear_sz;
756 unsigned int num_cams;
757
758 /* use a quarter of the TLBCAM for bolted linear map */
759 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
760
761 linear_sz = map_mem_in_cams(first_memblock_size, num_cams,

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