| reg.h (861604614a94a7aabc111e4a18aaf5d56d270e8a) | reg.h (5d506f159b2b9d0c9bee9bb43ccafb4f291143c2) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Contains the definition of registers common to all PowerPC variants. 4 * If a register definition has been changed in a different PowerPC 5 * variant, we will case it in #ifndef XXX ... #endif, and have the 6 * number used in the Programming Environments Manual For 32-Bit 7 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 8 */ --- 459 unchanged lines hidden (view full) --- 468#define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */ 469#define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */ 470#define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */ 471#define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */ 472#define LPCR_HR ASM_CONST(0x0000000000100000) 473#ifndef SPRN_LPID 474#define SPRN_LPID 0x13F /* Logical Partition Identifier */ 475#endif | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Contains the definition of registers common to all PowerPC variants. 4 * If a register definition has been changed in a different PowerPC 5 * variant, we will case it in #ifndef XXX ... #endif, and have the 6 * number used in the Programming Environments Manual For 32-Bit 7 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 8 */ --- 459 unchanged lines hidden (view full) --- 468#define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */ 469#define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */ 470#define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */ 471#define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */ 472#define LPCR_HR ASM_CONST(0x0000000000100000) 473#ifndef SPRN_LPID 474#define SPRN_LPID 0x13F /* Logical Partition Identifier */ 475#endif |
| 476#define LPID_RSVD_POWER7 0x3ff /* Reserved LPID for partn switching */ 477#define LPID_RSVD 0xfff /* Reserved LPID for partn switching */ | |
| 478#define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */ 479#define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */ 480#define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */ 481#define SPRN_PCR 0x152 /* Processor compatibility register */ 482#define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */ 483#define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */ 484#define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */ 485#define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */ --- 978 unchanged lines hidden --- | 476#define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */ 477#define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */ 478#define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */ 479#define SPRN_PCR 0x152 /* Processor compatibility register */ 480#define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */ 481#define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */ 482#define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */ 483#define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */ --- 978 unchanged lines hidden --- |