mpic.h (a9de18eb761f7c1c860964b2e5addc1a35c7e861) mpic.h (d91e4ea7047d96733d763f1626f1f21ff4298cef)
1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <linux/sysdev.h>
7#include <asm/dcr.h>
8#include <asm/msi_bitmap.h>

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17#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
18#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
19#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
20#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
21#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22#define MPIC_GREG_FEATURE_1 0x00010
23#define MPIC_GREG_GLOBAL_CONF_0 0x00020
24#define MPIC_GREG_GCONF_RESET 0x80000000
1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <linux/sysdev.h>
7#include <asm/dcr.h>
8#include <asm/msi_bitmap.h>

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17#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
18#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
19#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
20#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
21#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22#define MPIC_GREG_FEATURE_1 0x00010
23#define MPIC_GREG_GLOBAL_CONF_0 0x00020
24#define MPIC_GREG_GCONF_RESET 0x80000000
25/* On the FSL mpic implementations the Mode field is expand to be
26 * 2 bits wide:
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
29 * 0b10 = reserved
30 * 0b11 = External proxy / coreint
31 */
32#define MPIC_GREG_GCONF_COREINT 0x60000000
25#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
26#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
27#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
28#define MPIC_GREG_GCONF_MCK 0x08000000
29#define MPIC_GREG_GLOBAL_CONF_1 0x00030
30#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
31#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
32#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \

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352/* Enable delivery of prio 15 interrupts as MCK instead of EE */
353#define MPIC_ENABLE_MCK 0x00000200
354/* Disable bias among target selection, spread interrupts evenly */
355#define MPIC_NO_BIAS 0x00000400
356/* Ignore NIRQS as reported by FRR */
357#define MPIC_BROKEN_FRR_NIRQS 0x00000800
358/* Destination only supports a single CPU at a time */
359#define MPIC_SINGLE_DEST_CPU 0x00001000
33#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
34#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
35#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
36#define MPIC_GREG_GCONF_MCK 0x08000000
37#define MPIC_GREG_GLOBAL_CONF_1 0x00030
38#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
39#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
40#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \

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360/* Enable delivery of prio 15 interrupts as MCK instead of EE */
361#define MPIC_ENABLE_MCK 0x00000200
362/* Disable bias among target selection, spread interrupts evenly */
363#define MPIC_NO_BIAS 0x00000400
364/* Ignore NIRQS as reported by FRR */
365#define MPIC_BROKEN_FRR_NIRQS 0x00000800
366/* Destination only supports a single CPU at a time */
367#define MPIC_SINGLE_DEST_CPU 0x00001000
368/* Enable CoreInt delivery of interrupts */
369#define MPIC_ENABLE_COREINT 0x00002000
360
361/* MPIC HW modification ID */
362#define MPIC_REGSET_MASK 0xf0000000
363#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
364#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
365
366#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
367#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */

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465extern void mpic_mask_irq(unsigned int irq);
466/* EOI a specific virq */
467extern void mpic_end_irq(unsigned int irq);
468
469/* Fetch interrupt from a given mpic */
470extern unsigned int mpic_get_one_irq(struct mpic *mpic);
471/* This one gets from the primary mpic */
472extern unsigned int mpic_get_irq(void);
370
371/* MPIC HW modification ID */
372#define MPIC_REGSET_MASK 0xf0000000
373#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
374#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
375
376#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
377#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */

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475extern void mpic_mask_irq(unsigned int irq);
476/* EOI a specific virq */
477extern void mpic_end_irq(unsigned int irq);
478
479/* Fetch interrupt from a given mpic */
480extern unsigned int mpic_get_one_irq(struct mpic *mpic);
481/* This one gets from the primary mpic */
482extern unsigned int mpic_get_irq(void);
483/* This one gets from the primary mpic via CoreInt*/
484extern unsigned int mpic_get_coreint_irq(void);
473/* Fetch Machine Check interrupt from primary mpic */
474extern unsigned int mpic_get_mcirq(void);
475
476/* Set the EPIC clock ratio */
477void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
478
479/* Enable/Disable EPIC serial interrupt mode */
480void mpic_set_serial_int(struct mpic *mpic, int enable);
481
482#endif /* __KERNEL__ */
483#endif /* _ASM_POWERPC_MPIC_H */
485/* Fetch Machine Check interrupt from primary mpic */
486extern unsigned int mpic_get_mcirq(void);
487
488/* Set the EPIC clock ratio */
489void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
490
491/* Enable/Disable EPIC serial interrupt mode */
492void mpic_set_serial_int(struct mpic *mpic, int enable);
493
494#endif /* __KERNEL__ */
495#endif /* _ASM_POWERPC_MPIC_H */