| cputable.h (6d2170be4561293a6aa821c773687bd3f18e8206) | cputable.h (7c03d653cd257793dc40520c94e229b5fd0578e7) |
|---|---|
| 1#ifndef __ASM_POWERPC_CPUTABLE_H 2#define __ASM_POWERPC_CPUTABLE_H 3 4#define PPC_FEATURE_32 0x80000000 5#define PPC_FEATURE_64 0x40000000 6#define PPC_FEATURE_601_INSTR 0x20000000 7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000 8#define PPC_FEATURE_HAS_FPU 0x08000000 --- 68 unchanged lines hidden (view full) --- 77struct cpu_spec { 78 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 79 unsigned int pvr_mask; 80 unsigned int pvr_value; 81 82 char *cpu_name; 83 unsigned long cpu_features; /* Kernel features */ 84 unsigned int cpu_user_features; /* Userland features */ | 1#ifndef __ASM_POWERPC_CPUTABLE_H 2#define __ASM_POWERPC_CPUTABLE_H 3 4#define PPC_FEATURE_32 0x80000000 5#define PPC_FEATURE_64 0x40000000 6#define PPC_FEATURE_601_INSTR 0x20000000 7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000 8#define PPC_FEATURE_HAS_FPU 0x08000000 --- 68 unchanged lines hidden (view full) --- 77struct cpu_spec { 78 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 79 unsigned int pvr_mask; 80 unsigned int pvr_value; 81 82 char *cpu_name; 83 unsigned long cpu_features; /* Kernel features */ 84 unsigned int cpu_user_features; /* Userland features */ |
| 85 unsigned int mmu_features; /* MMU features */ |
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| 85 86 /* cache line sizes */ 87 unsigned int icache_bsize; 88 unsigned int dcache_bsize; 89 90 /* number of performance monitor counters */ 91 unsigned int num_pmcs; 92 enum powerpc_pmc_type pmc_type; --- 46 unchanged lines hidden (view full) --- 139#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) 140#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) 141#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) 142#define CPU_FTR_TAU ASM_CONST(0x0000000000000010) 143#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) 144#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) 145#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080) 146#define CPU_FTR_601 ASM_CONST(0x0000000000000100) | 86 87 /* cache line sizes */ 88 unsigned int icache_bsize; 89 unsigned int dcache_bsize; 90 91 /* number of performance monitor counters */ 92 unsigned int num_pmcs; 93 enum powerpc_pmc_type pmc_type; --- 46 unchanged lines hidden (view full) --- 140#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) 141#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) 142#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) 143#define CPU_FTR_TAU ASM_CONST(0x0000000000000010) 144#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) 145#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) 146#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080) 147#define CPU_FTR_601 ASM_CONST(0x0000000000000100) |
| 147#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200) | |
| 148#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) 149#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) 150#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) 151#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) 152#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) 153#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) | 148#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) 149#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) 150#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) 151#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) 152#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) 153#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) |
| 154#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000) | |
| 155#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) 156#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | 154#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) 155#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) |
| 157#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) | |
| 158#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 159#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 160#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 161#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) 162#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) 163#define CPU_FTR_SPE ASM_CONST(0x0000000002000000) 164#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000) 165#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000) --- 95 unchanged lines hidden (view full) --- 261#define CPU_FTR_MAYBE_CAN_DOZE 0 262#define CPU_FTR_MAYBE_CAN_NAP 0 263#endif 264 265#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ 266 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ 267 !defined(CONFIG_BOOKE)) 268 | 156#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 157#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 158#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 159#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) 160#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) 161#define CPU_FTR_SPE ASM_CONST(0x0000000002000000) 162#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000) 163#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000) --- 95 unchanged lines hidden (view full) --- 259#define CPU_FTR_MAYBE_CAN_DOZE 0 260#define CPU_FTR_MAYBE_CAN_NAP 0 261#endif 262 263#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ 264 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ 265 !defined(CONFIG_BOOKE)) 266 |
| 269#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \ | 267#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ |
| 270 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 271#define CPU_FTRS_603 (CPU_FTR_COMMON | \ 272 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 273 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 274#define CPU_FTRS_604 (CPU_FTR_COMMON | \ | 268 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 269#define CPU_FTRS_603 (CPU_FTR_COMMON | \ 270 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 271 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 272#define CPU_FTRS_604 (CPU_FTR_COMMON | \ |
| 275 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE) | 273 CPU_FTR_USE_TB | CPU_FTR_PPC_LE) |
| 276#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 277 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 274#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 275 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 278 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
| 279#define CPU_FTRS_740 (CPU_FTR_COMMON | \ 280 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 277#define CPU_FTRS_740 (CPU_FTR_COMMON | \ 278 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 281 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 279 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ |
| 282 CPU_FTR_PPC_LE) 283#define CPU_FTRS_750 (CPU_FTR_COMMON | \ 284 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 280 CPU_FTR_PPC_LE) 281#define CPU_FTRS_750 (CPU_FTR_COMMON | \ 282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 285 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 283 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ |
| 286 CPU_FTR_PPC_LE) | 284 CPU_FTR_PPC_LE) |
| 287#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS) | 285#define CPU_FTRS_750CL (CPU_FTRS_750) |
| 288#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 289#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) | 286#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 287#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) |
| 290#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \ 291 CPU_FTR_HAS_HIGH_BATS) | 288#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) |
| 292#define CPU_FTRS_750GX (CPU_FTRS_750FX) 293#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 294 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 289#define CPU_FTRS_750GX (CPU_FTRS_750FX) 290#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 291 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 295 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 292 CPU_FTR_ALTIVEC_COMP | \ |
| 296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 297#define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 298 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 293 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 294#define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 295 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
| 299 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 296 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ |
| 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 301#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 302 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 297 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 298#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 299 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 303 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 300 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
| 304 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 305#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 306 CPU_FTR_USE_TB | \ 307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 301 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 302#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 303 CPU_FTR_USE_TB | \ 304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 308 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 305 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
| 309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 311#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 312 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 306 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 307 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 308#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 309 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 310 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 314 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 311 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
| 315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 316#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 317 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 318 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ | 312 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 313#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 314 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 315 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
| 319 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ 320 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 316 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 321#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 322 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 323 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 317#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 318 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 324 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 320 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
| 325 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 321 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
| 326 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) | 322 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
| 327#define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 328 CPU_FTR_USE_TB | \ 329 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 323#define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 324 CPU_FTR_USE_TB | \ 325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 330 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 331 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 326 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
| 332 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 333#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 334 CPU_FTR_USE_TB | \ 335 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 327 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 328#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 329 CPU_FTR_USE_TB | \ 330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 336 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 337 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 331 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
| 338 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 339 CPU_FTR_NEED_PAIRED_STWCX) 340#define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 341 CPU_FTR_USE_TB | \ 342 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 332 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 333 CPU_FTR_NEED_PAIRED_STWCX) 334#define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 335 CPU_FTR_USE_TB | \ 336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 343 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 344 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 337 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
| 345 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 346#define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 347 CPU_FTR_USE_TB | \ 348 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 338 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 339#define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 340 CPU_FTR_USE_TB | \ 341 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 349 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 350 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 342 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
| 351 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 352#define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 353 CPU_FTR_USE_TB | \ 354 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 343 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 344#define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 345 CPU_FTR_USE_TB | \ 346 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
| 355 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ 356 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | 347 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
| 357 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 358#define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 359 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 360#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ | 348 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 349#define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 350 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 351#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ |
| 361 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) | 352 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) |
| 362#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ | 353#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ |
| 363 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | 354 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ |
| 364 CPU_FTR_COMMON) 365#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ | 355 CPU_FTR_COMMON) 356#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ |
| 366 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | 357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ |
| 367 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) | 358 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) |
| 368#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \ 369 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) | 359#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) |
| 370#define CPU_FTRS_8XX (CPU_FTR_USE_TB) 371#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 372#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 373#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 374 CPU_FTR_INDEXED_DCR) 375#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 376 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 377 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE) 378#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 379 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 380 CPU_FTR_NOEXECUTE) 381#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | 360#define CPU_FTRS_8XX (CPU_FTR_USE_TB) 361#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 362#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 363#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 364 CPU_FTR_INDEXED_DCR) 365#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 366 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 367 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE) 368#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 369 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 370 CPU_FTR_NOEXECUTE) 371#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
| 382 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \ | 372 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ |
| 383 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 384#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | 373 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 374#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
| 385 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \ | 375 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ |
| 386 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE) 387#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 388 389/* 64-bit CPUs */ 390#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 376 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE) 377#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 378 379/* 64-bit CPUs */ 380#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 391 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) | 381 CPU_FTR_IABR | CPU_FTR_PPC_LE) |
| 392#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 382#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 393 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ | 383 CPU_FTR_IABR | \ |
| 394 CPU_FTR_MMCRA | CPU_FTR_CTRL) 395#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 384 CPU_FTR_MMCRA | CPU_FTR_CTRL) 385#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 396 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 386 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 397 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ) 398#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 387 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ) 388#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 399 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 389 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 400 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 401 CPU_FTR_CP_USE_DCBTZ) 402#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 390 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 391 CPU_FTR_CP_USE_DCBTZ) 392#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 403 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 393 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 404 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 405 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 406 CPU_FTR_PURR) 407#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 394 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 395 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 396 CPU_FTR_PURR) 397#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 408 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 398 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 409 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 410 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 411 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 412 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD) 413#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 399 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 400 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 401 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 402 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD) 403#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 414 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 415 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 416 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 417 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 418 CPU_FTR_DSCR | CPU_FTR_SAO) 419#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 405 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 406 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 407 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 408 CPU_FTR_DSCR | CPU_FTR_SAO) 409#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 420 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 410 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
| 421 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 422 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \ 423 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 424 CPU_FTR_UNALIGNED_LD_STD) 425#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 411 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 412 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \ 413 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 414 CPU_FTR_UNALIGNED_LD_STD) 415#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
| 426 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 416 CPU_FTR_PPCAS_ARCH_V2 | \ |
| 427 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ 428 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B) | 417 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ 418 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B) |
| 429#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \ 430 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) | 419#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) |
| 431 432#ifdef __powerpc64__ 433#define CPU_FTRS_POSSIBLE \ 434 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 435 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 436 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 437 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX) 438#else --- 86 unchanged lines hidden --- | 420 421#ifdef __powerpc64__ 422#define CPU_FTRS_POSSIBLE \ 423 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 424 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 425 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 426 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX) 427#else --- 86 unchanged lines hidden --- |