cache.h (8c57a5e7b2820f349c95b8c8393fec1e0f4070d2) cache.h (f4329f2ecb149282fdfdd8830a936a56b1497a05)
1#ifndef _ASM_POWERPC_CACHE_H
2#define _ASM_POWERPC_CACHE_H
3
4#ifdef __KERNEL__
5
6
7/* bytes per L1 cache line */
8#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)

--- 6 unchanged lines hidden (view full) ---

15#define MAX_COPY_PREFETCH 4
16#if defined(CONFIG_PPC_47x)
17#define L1_CACHE_SHIFT 7
18#else
19#define L1_CACHE_SHIFT 5
20#endif
21#else /* CONFIG_PPC64 */
22#define L1_CACHE_SHIFT 7
1#ifndef _ASM_POWERPC_CACHE_H
2#define _ASM_POWERPC_CACHE_H
3
4#ifdef __KERNEL__
5
6
7/* bytes per L1 cache line */
8#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)

--- 6 unchanged lines hidden (view full) ---

15#define MAX_COPY_PREFETCH 4
16#if defined(CONFIG_PPC_47x)
17#define L1_CACHE_SHIFT 7
18#else
19#define L1_CACHE_SHIFT 5
20#endif
21#else /* CONFIG_PPC64 */
22#define L1_CACHE_SHIFT 7
23#define IFETCH_ALIGN_SHIFT 4 /* POWER8,9 */
23#endif
24
25#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
26
27#define SMP_CACHE_BYTES L1_CACHE_BYTES
28
24#endif
25
26#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
27
28#define SMP_CACHE_BYTES L1_CACHE_BYTES
29
30#define IFETCH_ALIGN_BYTES (1 << IFETCH_ALIGN_SHIFT)
31
29#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
30struct ppc64_caches {
31 u32 dsize; /* L1 d-cache size */
32 u32 dline_size; /* L1 d-cache line size */
33 u32 log_dline_size;
34 u32 dlines_per_page;
35 u32 isize; /* L1 i-cache size */
36 u32 iline_size; /* L1 i-cache line size */

--- 57 unchanged lines hidden --- 		32#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
33struct ppc64_caches {
34 u32 dsize; /* L1 d-cache size */
35 u32 dline_size; /* L1 d-cache line size */
36 u32 log_dline_size;
37 u32 dlines_per_page;
38 u32 isize; /* L1 i-cache size */
39 u32 iline_size; /* L1 i-cache line size */

--- 57 unchanged lines hidden ---