lite5200.dts (f0c8ac8083cbd9347b398bfddcca20f1e2786016) lite5200.dts (1b3c5cdab49a605f0e048e1ccbf4cc61a2626485)
1/*
2 * Lite5200 board Device Tree Source
3 *
4 * Copyright 2006-2007 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the

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177
178 gpio-wkup@c00 {
179 compatible = "mpc5200-gpio-wkup";
180 reg = <c00 40>;
181 interrupts = <1 8 0 0 3 0>;
182 interrupt-parent = <&mpc5200_pic>;
183 };
184
1/*
2 * Lite5200 board Device Tree Source
3 *
4 * Copyright 2006-2007 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the

--- 168 unchanged lines hidden (view full) ---

177
178 gpio-wkup@c00 {
179 compatible = "mpc5200-gpio-wkup";
180 reg = <c00 40>;
181 interrupts = <1 8 0 0 3 0>;
182 interrupt-parent = <&mpc5200_pic>;
183 };
184
185 pci@0d00 {
186 #interrupt-cells = <1>;
187 #size-cells = <2>;
188 #address-cells = <3>;
189 device_type = "pci";
190 compatible = "mpc5200-pci";
191 reg = <d00 100>;
192 interrupt-map-mask = <f800 0 0 7>;
193 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
194 c000 0 0 2 &mpc5200_pic 0 0 3
195 c000 0 0 3 &mpc5200_pic 0 0 3
196 c000 0 0 4 &mpc5200_pic 0 0 3>;
197 clock-frequency = <0>; // From boot loader
198 interrupts = <2 8 0 2 9 0 2 a 0>;
199 interrupt-parent = <&mpc5200_pic>;
200 bus-range = <0 0>;
201 ranges = <42000000 0 80000000 80000000 0 20000000
202 02000000 0 a0000000 a0000000 0 10000000
203 01000000 0 00000000 b0000000 0 01000000>;
204 };
205
206 spi@f00 {
207 device_type = "spi";
208 compatible = "mpc5200-spi";
209 reg = <f00 20>;
210 interrupts = <2 d 0 2 e 0>;
211 interrupt-parent = <&mpc5200_pic>;
212 };
213

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332 fsl5200-clocking;
333 };
334 sram@8000 {
335 device_type = "sram";
336 compatible = "mpc5200-sram\0sram";
337 reg = <8000 4000>;
338 };
339 };
185 spi@f00 {
186 device_type = "spi";
187 compatible = "mpc5200-spi";
188 reg = <f00 20>;
189 interrupts = <2 d 0 2 e 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 };
192

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311 fsl5200-clocking;
312 };
313 sram@8000 {
314 device_type = "sram";
315 compatible = "mpc5200-sram\0sram";
316 reg = <8000 4000>;
317 };
318 };
319
320 pci@f0000d00 {
321 #interrupt-cells = <1>;
322 #size-cells = <2>;
323 #address-cells = <3>;
324 device_type = "pci";
325 compatible = "mpc5200-pci";
326 reg = <f0000d00 100>;
327 interrupt-map-mask = <f800 0 0 7>;
328 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
329 c000 0 0 2 &mpc5200_pic 0 0 3
330 c000 0 0 3 &mpc5200_pic 0 0 3
331 c000 0 0 4 &mpc5200_pic 0 0 3>;
332 clock-frequency = <0>; // From boot loader
333 interrupts = <2 8 0 2 9 0 2 a 0>;
334 interrupt-parent = <&mpc5200_pic>;
335 bus-range = <0 0>;
336 ranges = <42000000 0 80000000 80000000 0 20000000
337 02000000 0 a0000000 a0000000 0 10000000
338 01000000 0 00000000 b0000000 0 01000000>;
339 };
340};
340};