perf.c (944d79559d154c12becde0dab327016cf438f46c) perf.c (cb6fc18e9ca615f03d18e60c49855b434ca2e51e)
1/*
2 * Parisc performance counters
3 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
4 *
5 * This code is derived, with permission, from HP/UX sources.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by

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63/* definition of RDR regs */
64struct rdr_tbl_ent {
65 uint16_t width;
66 uint8_t num_words;
67 uint8_t write_control;
68};
69
70static int perf_processor_interface __read_mostly = UNKNOWN_INTF;
1/*
2 * Parisc performance counters
3 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
4 *
5 * This code is derived, with permission, from HP/UX sources.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by

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63/* definition of RDR regs */
64struct rdr_tbl_ent {
65 uint16_t width;
66 uint8_t num_words;
67 uint8_t write_control;
68};
69
70static int perf_processor_interface __read_mostly = UNKNOWN_INTF;
71static int perf_enabled __read_mostly = 0;
71static int perf_enabled __read_mostly;
72static spinlock_t perf_lock;
72static spinlock_t perf_lock;
73struct parisc_device *cpu_device __read_mostly = NULL;
73struct parisc_device *cpu_device __read_mostly;
74
75/* RDRs to write for PCX-W */
74
75/* RDRs to write for PCX-W */
76static int perf_rdrs_W[] =
76static const int perf_rdrs_W[] =
77 { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
78
79/* RDRs to write for PCX-U */
77 { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
78
79/* RDRs to write for PCX-U */
80static int perf_rdrs_U[] =
80static const int perf_rdrs_U[] =
81 { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
82
83/* RDR register descriptions for PCX-W */
81 { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
82
83/* RDR register descriptions for PCX-W */
84static struct rdr_tbl_ent perf_rdr_tbl_W[] = {
84static const struct rdr_tbl_ent perf_rdr_tbl_W[] = {
85 { 19, 1, 8 }, /* RDR 0 */
86 { 16, 1, 16 }, /* RDR 1 */
87 { 72, 2, 0 }, /* RDR 2 */
88 { 81, 2, 0 }, /* RDR 3 */
89 { 328, 6, 0 }, /* RDR 4 */
90 { 160, 3, 0 }, /* RDR 5 */
91 { 336, 6, 0 }, /* RDR 6 */
92 { 164, 3, 0 }, /* RDR 7 */

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112 { 18, 1, 0 }, /* RDR 27 */
113 { 128, 2, 0 }, /* RDR 28 */
114 { 0, 0, 0 }, /* RDR 29 */
115 { 16, 1, 0 }, /* RDR 30 */
116 { 16, 1, 0 }, /* RDR 31 */
117};
118
119/* RDR register descriptions for PCX-U */
85 { 19, 1, 8 }, /* RDR 0 */
86 { 16, 1, 16 }, /* RDR 1 */
87 { 72, 2, 0 }, /* RDR 2 */
88 { 81, 2, 0 }, /* RDR 3 */
89 { 328, 6, 0 }, /* RDR 4 */
90 { 160, 3, 0 }, /* RDR 5 */
91 { 336, 6, 0 }, /* RDR 6 */
92 { 164, 3, 0 }, /* RDR 7 */

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112 { 18, 1, 0 }, /* RDR 27 */
113 { 128, 2, 0 }, /* RDR 28 */
114 { 0, 0, 0 }, /* RDR 29 */
115 { 16, 1, 0 }, /* RDR 30 */
116 { 16, 1, 0 }, /* RDR 31 */
117};
118
119/* RDR register descriptions for PCX-U */
120static struct rdr_tbl_ent perf_rdr_tbl_U[] = {
120static const struct rdr_tbl_ent perf_rdr_tbl_U[] = {
121 { 19, 1, 8 }, /* RDR 0 */
122 { 32, 1, 16 }, /* RDR 1 */
123 { 20, 1, 0 }, /* RDR 2 */
124 { 0, 0, 0 }, /* RDR 3 */
125 { 344, 6, 0 }, /* RDR 4 */
126 { 176, 3, 0 }, /* RDR 5 */
127 { 336, 6, 0 }, /* RDR 6 */
128 { 0, 0, 0 }, /* RDR 7 */

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151 { 24, 1, 0 }, /* RDR 30 */
152 { 16, 1, 0 }, /* RDR 31 */
153};
154
155/*
156 * A non-zero write_control in the above tables is a byte offset into
157 * this array.
158 */
121 { 19, 1, 8 }, /* RDR 0 */
122 { 32, 1, 16 }, /* RDR 1 */
123 { 20, 1, 0 }, /* RDR 2 */
124 { 0, 0, 0 }, /* RDR 3 */
125 { 344, 6, 0 }, /* RDR 4 */
126 { 176, 3, 0 }, /* RDR 5 */
127 { 336, 6, 0 }, /* RDR 6 */
128 { 0, 0, 0 }, /* RDR 7 */

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151 { 24, 1, 0 }, /* RDR 30 */
152 { 16, 1, 0 }, /* RDR 31 */
153};
154
155/*
156 * A non-zero write_control in the above tables is a byte offset into
157 * this array.
158 */
159static uint64_t perf_bitmasks[] = {
159static const uint64_t perf_bitmasks[] = {
160 0x0000000000000000ul, /* first dbl word must be zero */
161 0xfdffe00000000000ul, /* RDR0 bitmask */
162 0x003f000000000000ul, /* RDR1 bitmask */
163 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */
164 0xfffffffffffffffful,
165 0xfffffffc00000000ul,
166 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */
167 0xfffffffffffffffful,
168 0xfffffffffffffffcul,
169 0xff00000000000000ul
170};
171
172/*
173 * Write control bitmasks for Pa-8700 processor given
174 * somethings have changed slightly.
175 */
160 0x0000000000000000ul, /* first dbl word must be zero */
161 0xfdffe00000000000ul, /* RDR0 bitmask */
162 0x003f000000000000ul, /* RDR1 bitmask */
163 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */
164 0xfffffffffffffffful,
165 0xfffffffc00000000ul,
166 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */
167 0xfffffffffffffffful,
168 0xfffffffffffffffcul,
169 0xff00000000000000ul
170};
171
172/*
173 * Write control bitmasks for Pa-8700 processor given
174 * somethings have changed slightly.
175 */
176static uint64_t perf_bitmasks_piranha[] = {
176static const uint64_t perf_bitmasks_piranha[] = {
177 0x0000000000000000ul, /* first dbl word must be zero */
178 0xfdffe00000000000ul, /* RDR0 bitmask */
179 0x003f000000000000ul, /* RDR1 bitmask */
180 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */
181 0xfffffffffffffffful,
182 0xfffffffc00000000ul,
183 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */
184 0xfffffffffffffffful,
185 0xfffffffffffffffful,
186 0xfffc000000000000ul
187};
188
177 0x0000000000000000ul, /* first dbl word must be zero */
178 0xfdffe00000000000ul, /* RDR0 bitmask */
179 0x003f000000000000ul, /* RDR1 bitmask */
180 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */
181 0xfffffffffffffffful,
182 0xfffffffc00000000ul,
183 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */
184 0xfffffffffffffffful,
185 0xfffffffffffffffful,
186 0xfffc000000000000ul
187};
188
189static uint64_t *bitmask_array; /* array of bitmasks to use */
189static const uint64_t *bitmask_array; /* array of bitmasks to use */
190
191/******************************************************************************
192 * Function Prototypes
193 *****************************************************************************/
194static int perf_config(uint32_t *image_ptr);
195static int perf_release(struct inode *inode, struct file *file);
196static int perf_open(struct inode *inode, struct file *file);
197static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos);
198static ssize_t perf_write(struct file *file, const char __user *buf, size_t count,
199 loff_t *ppos);
200static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
201static void perf_start_counters(void);
202static int perf_stop_counters(uint32_t *raddr);
190
191/******************************************************************************
192 * Function Prototypes
193 *****************************************************************************/
194static int perf_config(uint32_t *image_ptr);
195static int perf_release(struct inode *inode, struct file *file);
196static int perf_open(struct inode *inode, struct file *file);
197static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos);
198static ssize_t perf_write(struct file *file, const char __user *buf, size_t count,
199 loff_t *ppos);
200static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
201static void perf_start_counters(void);
202static int perf_stop_counters(uint32_t *raddr);
203static struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);
203static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);
204static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer);
205static int perf_rdr_clear(uint32_t rdr_num);
206static int perf_write_image(uint64_t *memaddr);
207static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);
208
209/* External Assembly Routines */
210extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);
211extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);

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650}
651
652/*
653 * perf_rdr_get_entry
654 *
655 * Retrieve a pointer to the description of what this
656 * RDR contains.
657 */
204static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer);
205static int perf_rdr_clear(uint32_t rdr_num);
206static int perf_write_image(uint64_t *memaddr);
207static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);
208
209/* External Assembly Routines */
210extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);
211extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);

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650}
651
652/*
653 * perf_rdr_get_entry
654 *
655 * Retrieve a pointer to the description of what this
656 * RDR contains.
657 */
658static struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num)
658static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num)
659{
660 if (perf_processor_interface == ONYX_INTF) {
661 return &perf_rdr_tbl_U[rdr_num];
662 } else {
663 return &perf_rdr_tbl_W[rdr_num];
664 }
665}
666
667/*
668 * perf_rdr_read_ubuf
669 *
670 * Read the RDR value into the buffer specified.
671 */
672static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer)
673{
674 uint64_t data, data_mask = 0;
675 uint32_t width, xbits, i;
659{
660 if (perf_processor_interface == ONYX_INTF) {
661 return &perf_rdr_tbl_U[rdr_num];
662 } else {
663 return &perf_rdr_tbl_W[rdr_num];
664 }
665}
666
667/*
668 * perf_rdr_read_ubuf
669 *
670 * Read the RDR value into the buffer specified.
671 */
672static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer)
673{
674 uint64_t data, data_mask = 0;
675 uint32_t width, xbits, i;
676 struct rdr_tbl_ent *tentry;
676 const struct rdr_tbl_ent *tentry;
677
678 tentry = perf_rdr_get_entry(rdr_num);
679 if ((width = tentry->width) == 0)
680 return 0;
681
682 /* Clear out buffer */
683 i = tentry->num_words;
684 while (i--) {

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716
717/*
718 * perf_rdr_clear
719 *
720 * Zero out the given RDR register
721 */
722static int perf_rdr_clear(uint32_t rdr_num)
723{
677
678 tentry = perf_rdr_get_entry(rdr_num);
679 if ((width = tentry->width) == 0)
680 return 0;
681
682 /* Clear out buffer */
683 i = tentry->num_words;
684 while (i--) {

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716
717/*
718 * perf_rdr_clear
719 *
720 * Zero out the given RDR register
721 */
722static int perf_rdr_clear(uint32_t rdr_num)
723{
724 struct rdr_tbl_ent *tentry;
724 const struct rdr_tbl_ent *tentry;
725 int32_t i;
726
727 tentry = perf_rdr_get_entry(rdr_num);
728
729 if (tentry->width == 0) {
730 return -1;
731 }
732

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748 *
749 * Write the given image out to the processor
750 */
751static int perf_write_image(uint64_t *memaddr)
752{
753 uint64_t buffer[MAX_RDR_WORDS];
754 uint64_t *bptr;
755 uint32_t dwords;
725 int32_t i;
726
727 tentry = perf_rdr_get_entry(rdr_num);
728
729 if (tentry->width == 0) {
730 return -1;
731 }
732

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748 *
749 * Write the given image out to the processor
750 */
751static int perf_write_image(uint64_t *memaddr)
752{
753 uint64_t buffer[MAX_RDR_WORDS];
754 uint64_t *bptr;
755 uint32_t dwords;
756 uint32_t *intrigue_rdr;
757 uint64_t *intrigue_bitmask, tmp64;
756 const uint32_t *intrigue_rdr;
757 const uint64_t *intrigue_bitmask;
758 uint64_t tmp64;
758 void __iomem *runway;
759 void __iomem *runway;
759 struct rdr_tbl_ent *tentry;
760 const struct rdr_tbl_ent *tentry;
760 int i;
761
762 /* Clear out counters */
763 if (perf_processor_interface == ONYX_INTF) {
764
765 perf_rdr_clear(16);
766
767 /* Toggle performance monitor */

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825/*
826 * perf_rdr_write
827 *
828 * Write the given RDR register with the contents
829 * of the given buffer.
830 */
831static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer)
832{
761 int i;
762
763 /* Clear out counters */
764 if (perf_processor_interface == ONYX_INTF) {
765
766 perf_rdr_clear(16);
767
768 /* Toggle performance monitor */

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826/*
827 * perf_rdr_write
828 *
829 * Write the given RDR register with the contents
830 * of the given buffer.
831 */
832static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer)
833{
833 struct rdr_tbl_ent *tentry;
834 const struct rdr_tbl_ent *tentry;
834 int32_t i;
835
836printk("perf_rdr_write\n");
837 tentry = perf_rdr_get_entry(rdr_num);
838 if (tentry->width == 0) { return; }
839
840 i = tentry->num_words;
841 while (i--) {
842 if (perf_processor_interface == ONYX_INTF) {
843 perf_rdr_shift_out_U(rdr_num, buffer[i]);
844 } else {
845 perf_rdr_shift_out_W(rdr_num, buffer[i]);
846 }
847 }
848printk("perf_rdr_write done\n");
849}
850
851module_init(perf_init);
835 int32_t i;
836
837printk("perf_rdr_write\n");
838 tentry = perf_rdr_get_entry(rdr_num);
839 if (tentry->width == 0) { return; }
840
841 i = tentry->num_words;
842 while (i--) {
843 if (perf_processor_interface == ONYX_INTF) {
844 perf_rdr_shift_out_U(rdr_num, buffer[i]);
845 } else {
846 perf_rdr_shift_out_W(rdr_num, buffer[i]);
847 }
848 }
849printk("perf_rdr_write done\n");
850}
851
852module_init(perf_init);