pci-rt2880.c (0cce284537fb42d9c28b9b31038ffc9b464555f5) pci-rt2880.c (19a8d6b7604df85402deecae01d7861cb1d40c89)
1/*
2 * Ralink RT288x SoC PCI register definitions
3 *
4 * Copyright (C) 2009 John Crispin <john@phrozen.org>
5 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Parts of this file are based on Ralink's 2.6.21 BSP
8 *

--- 167 unchanged lines hidden (view full) ---

176 address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
177
178 spin_lock_irqsave(&rt2880_pci_lock, flags);
179 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
180 rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
181 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
182}
183
1/*
2 * Ralink RT288x SoC PCI register definitions
3 *
4 * Copyright (C) 2009 John Crispin <john@phrozen.org>
5 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Parts of this file are based on Ralink's 2.6.21 BSP
8 *

--- 167 unchanged lines hidden (view full) ---

176 address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
177
178 spin_lock_irqsave(&rt2880_pci_lock, flags);
179 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
180 rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
181 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
182}
183
184int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
184int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
185{
186 u16 cmd;
187 int irq = -1;
188
189 if (dev->bus->number != 0)
190 return irq;
191
192 switch (PCI_SLOT(dev->devfn)) {

--- 89 unchanged lines hidden --- 		185{
186 u16 cmd;
187 int irq = -1;
188
189 if (dev->bus->number != 0)
190 return irq;
191
192 switch (PCI_SLOT(dev->devfn)) {

--- 89 unchanged lines hidden ---