pci-mt7620.c (e9331ee9b164d58b4dd0abc882ba7e23d2f404b3) pci-mt7620.c (19a8d6b7604df85402deecae01d7861cb1d40c89)
1/*
2 * Ralink MT7620A SoC PCI support
3 *
4 * Copyright (C) 2007-2013 Bruce Chang (Mediatek)
5 * Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published

--- 347 unchanged lines hidden (view full) ---

356 pci_config_write(NULL, 0, 4, 4, val | 0x7);
357
358 pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
359 register_pci_controller(&mt7620_controller);
360
361 return 0;
362}
363
1/*
2 * Ralink MT7620A SoC PCI support
3 *
4 * Copyright (C) 2007-2013 Bruce Chang (Mediatek)
5 * Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published

--- 347 unchanged lines hidden (view full) ---

356 pci_config_write(NULL, 0, 4, 4, val | 0x7);
357
358 pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
359 register_pci_controller(&mt7620_controller);
360
361 return 0;
362}
363
364int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
364int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
365{
366 u16 cmd;
367 u32 val;
368 int irq = 0;
369
370 if ((dev->bus->number == 0) && (slot == 0)) {
371 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
372 pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,

--- 51 unchanged lines hidden --- 		365{
366 u16 cmd;
367 u32 val;
368 int irq = 0;
369
370 if ((dev->bus->number == 0) && (slot == 0)) {
371 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
372 pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,

--- 51 unchanged lines hidden ---