pci-bcm63xx.c (f2d1035e956052d29c83fe8f8da0d056af6d221a) pci-bcm63xx.c (ba00e2e5c24f447fb09437a99df697787103f0cd)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/clk.h>
15#include <asm/bootinfo.h>
16
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/clk.h>
15#include <asm/bootinfo.h>
16
17#include <bcm63xx_reset.h>
18
17#include "pci-bcm63xx.h"
18
19/*
20 * Allow PCI to be disabled at runtime depending on board nvram
21 * configuration
22 */
23int bcm63xx_pci_enabled;
24

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121 u32 val;
122
123 /* enable SERDES */
124 val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
125 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
126 bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
127
128 /* reset the PCIe core */
19#include "pci-bcm63xx.h"
20
21/*
22 * Allow PCI to be disabled at runtime depending on board nvram
23 * configuration
24 */
25int bcm63xx_pci_enabled;
26

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123 u32 val;
124
125 /* enable SERDES */
126 val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
127 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
128 bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
129
130 /* reset the PCIe core */
129 val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
130
131 val &= ~SOFTRESET_6328_PCIE_MASK;
132 val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
133 val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
134 val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
135 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
131 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
132 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
136 mdelay(10);
137
133 mdelay(10);
134
138 val |= SOFTRESET_6328_PCIE_MASK;
139 val |= SOFTRESET_6328_PCIE_CORE_MASK;
140 val |= SOFTRESET_6328_PCIE_HARD_MASK;
141 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
135 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
142 mdelay(10);
143
136 mdelay(10);
137
144 val |= SOFTRESET_6328_PCIE_EXT_MASK;
145 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
138 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
146 mdelay(200);
147}
148
149static struct clk *pcie_clk;
150
151static int __init bcm63xx_register_pcie(void)
152{
153 u32 val;

--- 197 unchanged lines hidden --- 		139 mdelay(200);
140}
141
142static struct clk *pcie_clk;
143
144static int __init bcm63xx_register_pcie(void)
145{
146 u32 val;

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