| uasm-mips.c (9d066a252786e1a18484a6283f82614d42a9f4ac) | uasm-mips.c (c29732a179c2ed0cb9f001a8dc07dcf432389313) |
|---|---|
| 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. --- 53 unchanged lines hidden (view full) --- 62 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, 63 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, 64 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 65#ifndef CONFIG_CPU_MIPSR6 66 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 67#else 68 { insn_cache, M6(cache_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 }, 69#endif | 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. --- 53 unchanged lines hidden (view full) --- 62 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, 63 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, 64 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 65#ifndef CONFIG_CPU_MIPSR6 66 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 67#else 68 { insn_cache, M6(cache_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 }, 69#endif |
| 70 { insn_cfc1, M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD }, 71 { insn_ctc1, M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD }, |
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| 70 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 71 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, 72 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, 73 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, 74 { insn_divu, M(spec_op, 0, 0, 0, 0, divu_op), RS | RT }, 75 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 76 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 77 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, --- 171 unchanged lines hidden --- | 72 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 73 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, 74 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE }, 75 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, 76 { insn_divu, M(spec_op, 0, 0, 0, 0, divu_op), RS | RT }, 77 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 78 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 79 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE }, --- 171 unchanged lines hidden --- |