| uasm-mips.c (390363ed77c05f4971254bebc96554afb79dd453) | uasm-mips.c (e8ef868b470984064c23ce4bf2cd4c0167e1fbe5) |
|---|---|
| 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. --- 93 unchanged lines hidden (view full) --- 102 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, 103 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, 104 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 105 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 106 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 107 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, 108 { insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD }, 109 { insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, | 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. --- 93 unchanged lines hidden (view full) --- 102 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, 103 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, 104 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 105 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 106 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 107 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, 108 { insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD }, 109 { insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| 110 { insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD }, |
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| 110 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, 111 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, 112 { insn_srlv, M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD }, 113 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, 114 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 115 { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE }, 116 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, 117 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, --- 96 unchanged lines hidden --- | 111 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, 112 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, 113 { insn_srlv, M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD }, 114 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, 115 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 116 { insn_sync, M(spec_op, 0, 0, 0, 0, sync_op), RE }, 117 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, 118 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, --- 96 unchanged lines hidden --- |