uasm-micromips.c (e5451c8f8330e03ad3cfa16048b4daf961af434f) uasm-micromips.c (c29732a179c2ed0cb9f001a8dc07dcf432389313)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.

--- 39 unchanged lines hidden (view full) ---

48 { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
49 { insn_beql, 0, 0 },
50 { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
51 { insn_bgezl, 0, 0 },
52 { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
53 { insn_bltzl, 0, 0 },
54 { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
55 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.

--- 39 unchanged lines hidden (view full) ---

48 { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
49 { insn_beql, 0, 0 },
50 { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
51 { insn_bgezl, 0, 0 },
52 { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
53 { insn_bltzl, 0, 0 },
54 { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
55 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
56 { insn_cfc1, M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS },
57 { insn_ctc1, M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS },
56 { insn_daddu, 0, 0 },
57 { insn_daddiu, 0, 0 },
58 { insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS },
59 { insn_dmfc0, 0, 0 },
60 { insn_dmtc0, 0, 0 },
61 { insn_dsll, 0, 0 },
62 { insn_dsll32, 0, 0 },
63 { insn_dsra, 0, 0 },

--- 97 unchanged lines hidden (view full) ---

161 }
162
163 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
164 panic("Unsupported Micro-assembler instruction %d", opc);
165
166 op = ip->match;
167 va_start(ap, opc);
168 if (ip->fields & RS) {
58 { insn_daddu, 0, 0 },
59 { insn_daddiu, 0, 0 },
60 { insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS },
61 { insn_dmfc0, 0, 0 },
62 { insn_dmtc0, 0, 0 },
63 { insn_dsll, 0, 0 },
64 { insn_dsll32, 0, 0 },
65 { insn_dsra, 0, 0 },

--- 97 unchanged lines hidden (view full) ---

163 }
164
165 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
166 panic("Unsupported Micro-assembler instruction %d", opc);
167
168 op = ip->match;
169 va_start(ap, opc);
170 if (ip->fields & RS) {
169 if (opc == insn_mfc0 || opc == insn_mtc0)
171 if (opc == insn_mfc0 || opc == insn_mtc0 ||
172 opc == insn_cfc1 || opc == insn_ctc1)
170 op |= build_rt(va_arg(ap, u32));
171 else
172 op |= build_rs(va_arg(ap, u32));
173 }
174 if (ip->fields & RT) {
173 op |= build_rt(va_arg(ap, u32));
174 else
175 op |= build_rs(va_arg(ap, u32));
176 }
177 if (ip->fields & RT) {
175 if (opc == insn_mfc0 || opc == insn_mtc0)
178 if (opc == insn_mfc0 || opc == insn_mtc0 ||
179 opc == insn_cfc1 || opc == insn_ctc1)
176 op |= build_rs(va_arg(ap, u32));
177 else
178 op |= build_rt(va_arg(ap, u32));
179 }
180 if (ip->fields & RD)
181 op |= build_rd(va_arg(ap, u32));
182 if (ip->fields & RE)
183 op |= build_re(va_arg(ap, u32));

--- 44 unchanged lines hidden --- 		180 op |= build_rs(va_arg(ap, u32));
181 else
182 op |= build_rt(va_arg(ap, u32));
183 }
184 if (ip->fields & RD)
185 op |= build_rd(va_arg(ap, u32));
186 if (ip->fields & RE)
187 op |= build_re(va_arg(ap, u32));

--- 44 unchanged lines hidden ---