tlbex.c (2f8d01a1475cfede058c6a92b5d3dad576da2827) tlbex.c (c2377a42cd7696022448bcebaa12b07427dc1038)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer

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335static int scratch_reg;
336static int pgd_reg;
337enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
338
339static struct work_registers build_get_work_registers(u32 **p)
340{
341 struct work_registers r;
342
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer

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335static int scratch_reg;
336static int pgd_reg;
337enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
338
339static struct work_registers build_get_work_registers(u32 **p)
340{
341 struct work_registers r;
342
343 int smp_processor_id_reg;
344 int smp_processor_id_sel;
345 int smp_processor_id_shift;
346
347 if (scratch_reg >= 0) {
348 /* Save in CPU local C0_KScratch? */
349 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
350 r.r1 = K0;
351 r.r2 = K1;
352 r.r3 = 1;
353 return r;
354 }
355
356 if (num_possible_cpus() > 1) {
343 if (scratch_reg >= 0) {
344 /* Save in CPU local C0_KScratch? */
345 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
346 r.r1 = K0;
347 r.r2 = K1;
348 r.r3 = 1;
349 return r;
350 }
351
352 if (num_possible_cpus() > 1) {
357#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
358 smp_processor_id_shift = 51;
359 smp_processor_id_reg = 20; /* XContext */
360 smp_processor_id_sel = 0;
361#else
362# ifdef CONFIG_32BIT
363 smp_processor_id_shift = 25;
364 smp_processor_id_reg = 4; /* Context */
365 smp_processor_id_sel = 0;
366# endif
367# ifdef CONFIG_64BIT
368 smp_processor_id_shift = 26;
369 smp_processor_id_reg = 4; /* Context */
370 smp_processor_id_sel = 0;
371# endif
372#endif
373 /* Get smp_processor_id */
353 /* Get smp_processor_id */
374 UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel);
375 UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift);
354 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
355 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
376
377 /* handler_reg_save index in K0 */
378 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
379
380 UASM_i_LA(p, K1, (long)&handler_reg_save);
381 UASM_i_ADDU(p, K0, K0, K1);
382 } else {
383 UASM_i_LA(p, K0, (long)&handler_reg_save);

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832 /* Clear lower 23 bits of context. */
833 uasm_i_dins(p, ptr, 0, 0, 23);
834
835 /* 1 0 1 0 1 << 6 xkphys cached */
836 uasm_i_ori(p, ptr, ptr, 0x540);
837 uasm_i_drotr(p, ptr, ptr, 11);
838 }
839#elif defined(CONFIG_SMP)
356
357 /* handler_reg_save index in K0 */
358 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
359
360 UASM_i_LA(p, K1, (long)&handler_reg_save);
361 UASM_i_ADDU(p, K0, K0, K1);
362 } else {
363 UASM_i_LA(p, K0, (long)&handler_reg_save);

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812 /* Clear lower 23 bits of context. */
813 uasm_i_dins(p, ptr, 0, 0, 23);
814
815 /* 1 0 1 0 1 << 6 xkphys cached */
816 uasm_i_ori(p, ptr, ptr, 0x540);
817 uasm_i_drotr(p, ptr, ptr, 11);
818 }
819#elif defined(CONFIG_SMP)
840# ifdef CONFIG_MIPS_MT_SMTC
841 /*
842 * SMTC uses TCBind value as "CPU" index
843 */
844 uasm_i_mfc0(p, ptr, C0_TCBIND);
845 uasm_i_dsrl_safe(p, ptr, ptr, 19);
846# else
847 /*
848 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
849 * stored in CONTEXT.
850 */
851 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
852 uasm_i_dsrl_safe(p, ptr, ptr, 23);
853# endif
820 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
821 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
854 UASM_i_LA_mostly(p, tmp, pgdc);
855 uasm_i_daddu(p, ptr, ptr, tmp);
856 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
857 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
858#else
859 UASM_i_LA_mostly(p, ptr, pgdc);
860 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
861#endif

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952 */
953static void __maybe_unused
954build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
955{
956 long pgdc = (long)pgd_current;
957
958 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
959#ifdef CONFIG_SMP
822 UASM_i_LA_mostly(p, tmp, pgdc);
823 uasm_i_daddu(p, ptr, ptr, tmp);
824 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
825 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
826#else
827 UASM_i_LA_mostly(p, ptr, pgdc);
828 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
829#endif

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920 */
921static void __maybe_unused
922build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
923{
924 long pgdc = (long)pgd_current;
925
926 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
927#ifdef CONFIG_SMP
960#ifdef CONFIG_MIPS_MT_SMTC
961 /*
962 * SMTC uses TCBind value as "CPU" index
963 */
964 uasm_i_mfc0(p, ptr, C0_TCBIND);
928 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
965 UASM_i_LA_mostly(p, tmp, pgdc);
929 UASM_i_LA_mostly(p, tmp, pgdc);
966 uasm_i_srl(p, ptr, ptr, 19);
967#else
968 /*
969 * smp_processor_id() << 2 is stored in CONTEXT.
970 */
971 uasm_i_mfc0(p, ptr, C0_CONTEXT);
972 UASM_i_LA_mostly(p, tmp, pgdc);
973 uasm_i_srl(p, ptr, ptr, 23);
974#endif
930 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
975 uasm_i_addu(p, ptr, tmp, ptr);
976#else
977 UASM_i_LA_mostly(p, ptr, pgdc);
978#endif
979 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
980 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
981 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
982 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);

--- 1290 unchanged lines hidden --- 		931 uasm_i_addu(p, ptr, tmp, ptr);
932#else
933 UASM_i_LA_mostly(p, ptr, pgdc);
934#endif
935 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
936 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
937 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
938 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);

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