proc.c (a96102be700f87283f168942cd09a2b30f86f324) proc.c (f8fa4811dbb264aef13f982e963389fd828b1ac0)
1/*
2 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
3 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
1/*
2 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
3 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2004 Maciej W. Rozycki
4 * Copyright (C) 2004 Maciej W. Rozycki
5 */
6#include <linux/delay.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/seq_file.h>
10#include <asm/bootinfo.h>
11#include <asm/cpu.h>
12#include <asm/cpu-features.h>

--- 46 unchanged lines hidden (view full) ---

59 if (cpu_has_watch) {
60 seq_printf(m, "count: %d, address/irw mask: [",
61 cpu_data[n].watch_reg_count);
62 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
63 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
64 cpu_data[n].watch_reg_masks[i]);
65 seq_printf(m, "]\n");
66 }
5 */
6#include <linux/delay.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/seq_file.h>
10#include <asm/bootinfo.h>
11#include <asm/cpu.h>
12#include <asm/cpu-features.h>

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59 if (cpu_has_watch) {
60 seq_printf(m, "count: %d, address/irw mask: [",
61 cpu_data[n].watch_reg_count);
62 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
63 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
64 cpu_data[n].watch_reg_masks[i]);
65 seq_printf(m, "]\n");
66 }
67 if (cpu_has_mips_r) {
68 seq_printf(m, "isa\t\t\t:");
69 if (cpu_has_mips_1)
70 seq_printf(m, "%s", "mips1");
71 if (cpu_has_mips_2)
72 seq_printf(m, "%s", " mips2");
73 if (cpu_has_mips_3)
74 seq_printf(m, "%s", " mips3");
75 if (cpu_has_mips_4)
76 seq_printf(m, "%s", " mips4");
77 if (cpu_has_mips_5)
78 seq_printf(m, "%s", " mips5");
79 if (cpu_has_mips32r1)
80 seq_printf(m, "%s", " mips32r1");
81 if (cpu_has_mips32r2)
82 seq_printf(m, "%s", " mips32r2");
83 if (cpu_has_mips64r1)
84 seq_printf(m, "%s", " mips64r1");
85 if (cpu_has_mips64r2)
86 seq_printf(m, "%s", " mips64r2");
87 seq_printf(m, "\n");
88 }
89
90 seq_printf(m, "ASEs implemented\t:");
91 if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
92 if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx");
93 if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d");
94 if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
95 if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
96 if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
97 if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
67
68 seq_printf(m, "ASEs implemented\t:");
69 if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
70 if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx");
71 if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d");
72 if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
73 if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
74 if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
75 if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
76 if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
98 seq_printf(m, "\n");
99
100 seq_printf(m, "shadow register sets\t: %d\n",
101 cpu_data[n].srsets);
102 seq_printf(m, "kscratch registers\t: %d\n",
103 hweight8(cpu_data[n].kscratch_mask));
104 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
105

--- 32 unchanged lines hidden --- 		77 seq_printf(m, "\n");
78
79 seq_printf(m, "shadow register sets\t: %d\n",
80 cpu_data[n].srsets);
81 seq_printf(m, "kscratch registers\t: %d\n",
82 hweight8(cpu_data[n].kscratch_mask));
83 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
84

--- 32 unchanged lines hidden ---