genex.S (e35a5e35e0f45209a45ec2fd6df90f5ac3a05992) genex.S (192ef366198ce16c0379100565cdc5b7bd68511f)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
10 */
11#include <linux/init.h>
12
13#include <asm/asm.h>
14#include <asm/asmmacro.h>
15#include <asm/cacheops.h>
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
10 */
11#include <linux/init.h>
12
13#include <asm/asm.h>
14#include <asm/asmmacro.h>
15#include <asm/cacheops.h>
16#include <asm/irqflags.h>
16#include <asm/regdef.h>
17#include <asm/fpregdef.h>
18#include <asm/mipsregs.h>
19#include <asm/stackframe.h>
20#include <asm/war.h>
21
22#define PANIC_PIC(msg) \
23 .set push; \

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123 END(except_vec3_r4000)
124
125 __FINIT
126
127 .align 5
128NESTED(handle_int, PT_SIZE, sp)
129 SAVE_ALL
130 CLI
17#include <asm/regdef.h>
18#include <asm/fpregdef.h>
19#include <asm/mipsregs.h>
20#include <asm/stackframe.h>
21#include <asm/war.h>
22
23#define PANIC_PIC(msg) \
24 .set push; \

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124 END(except_vec3_r4000)
125
126 __FINIT
127
128 .align 5
129NESTED(handle_int, PT_SIZE, sp)
130 SAVE_ALL
131 CLI
132 TRACE_IRQS_OFF
131
132 PTR_LA ra, ret_from_irq
133 move a0, sp
134 j plat_irq_dispatch
135 END(handle_int)
136
137 __INIT
138

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211 mfc0 t2, CP0_TCCONTEXT
212 or t0, t0, t2
213 mtc0 t0, CP0_TCCONTEXT
214 xor t1, t1, t0
215 mtc0 t1, CP0_STATUS
216 _ehb
217#endif /* CONFIG_MIPS_MT_SMTC */
218 CLI
133
134 PTR_LA ra, ret_from_irq
135 move a0, sp
136 j plat_irq_dispatch
137 END(handle_int)
138
139 __INIT
140

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213 mfc0 t2, CP0_TCCONTEXT
214 or t0, t0, t2
215 mtc0 t0, CP0_TCCONTEXT
216 xor t1, t1, t0
217 mtc0 t1, CP0_STATUS
218 _ehb
219#endif /* CONFIG_MIPS_MT_SMTC */
220 CLI
221 TRACE_IRQS_OFF
219 move a0, sp
220 jalr v0
221 j ret_from_irq
222 END(except_vec_vi_handler)
223
224/*
225 * EJTAG debug exception handler.
226 */

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283 eret
284 .set pop
285 END(nmi_handler)
286
287 .macro __build_clear_none
288 .endm
289
290 .macro __build_clear_sti
222 move a0, sp
223 jalr v0
224 j ret_from_irq
225 END(except_vec_vi_handler)
226
227/*
228 * EJTAG debug exception handler.
229 */

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286 eret
287 .set pop
288 END(nmi_handler)
289
290 .macro __build_clear_none
291 .endm
292
293 .macro __build_clear_sti
294 TRACE_IRQS_ON
291 STI
292 .endm
293
294 .macro __build_clear_cli
295 CLI
295 STI
296 .endm
297
298 .macro __build_clear_cli
299 CLI
300 TRACE_IRQS_OFF
296 .endm
297
298 .macro __build_clear_fpe
299 cfc1 a1, fcr31
300 li a2, ~(0x3f << 12)
301 and a2, a1
302 ctc1 a2, fcr31
301 .endm
302
303 .macro __build_clear_fpe
304 cfc1 a1, fcr31
305 li a2, ~(0x3f << 12)
306 and a2, a1
307 ctc1 a2, fcr31
308 TRACE_IRQS_ON
303 STI
304 .endm
305
306 .macro __build_clear_ade
307 MFC0 t0, CP0_BADVADDR
308 PTR_S t0, PT_BVADDR(sp)
309 KMODE
310 .endm

--- 68 unchanged lines hidden --- 		309 STI
310 .endm
311
312 .macro __build_clear_ade
313 MFC0 t0, CP0_BADVADDR
314 PTR_S t0, PT_BVADDR(sp)
315 KMODE
316 .endm

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