cpu-probe.c (d75e2c9ad97c40f6d2cdaf2e16381b2034d19a6f) cpu-probe.c (2fa36399e63c911134f28b6878aada9b395c4209)
1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *

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185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC:
1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *

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185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC:
193 case CPU_LOONGSON1:
193 case CPU_XLR:
194 case CPU_XLP:
195 cpu_wait = r4k_wait;
196 break;
197
198 case CPU_RM7000:
199 cpu_wait = rm7k_wait_irqoff;
200 break;

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325{
326#ifdef __NEED_VMBITS_PROBE
327 write_c0_entryhi(0x3fffffffffffe000ULL);
328 back_to_back_c0_hazard();
329 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
330#endif
331}
332
194 case CPU_XLR:
195 case CPU_XLP:
196 cpu_wait = r4k_wait;
197 break;
198
199 case CPU_RM7000:
200 cpu_wait = rm7k_wait_irqoff;
201 break;

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326{
327#ifdef __NEED_VMBITS_PROBE
328 write_c0_entryhi(0x3fffffffffffe000ULL);
329 back_to_back_c0_hazard();
330 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
331#endif
332}
333
334static char unknown_isa[] __cpuinitdata = KERN_ERR \
335 "Unsupported ISA type, c0.config0: %d.";
336
337static inline unsigned int decode_config0(struct cpuinfo_mips *c)
338{
339 unsigned int config0;
340 int isa;
341
342 config0 = read_c0_config();
343
344 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
345 c->options |= MIPS_CPU_TLB;
346 isa = (config0 & MIPS_CONF_AT) >> 13;
347 switch (isa) {
348 case 0:
349 switch ((config0 & MIPS_CONF_AR) >> 10) {
350 case 0:
351 c->isa_level = MIPS_CPU_ISA_M32R1;
352 break;
353 case 1:
354 c->isa_level = MIPS_CPU_ISA_M32R2;
355 break;
356 default:
357 goto unknown;
358 }
359 break;
360 case 2:
361 switch ((config0 & MIPS_CONF_AR) >> 10) {
362 case 0:
363 c->isa_level = MIPS_CPU_ISA_M64R1;
364 break;
365 case 1:
366 c->isa_level = MIPS_CPU_ISA_M64R2;
367 break;
368 default:
369 goto unknown;
370 }
371 break;
372 default:
373 goto unknown;
374 }
375
376 return config0 & MIPS_CONF_M;
377
378unknown:
379 panic(unknown_isa, config0);
380}
381
382static inline unsigned int decode_config1(struct cpuinfo_mips *c)
383{
384 unsigned int config1;
385
386 config1 = read_c0_config1();
387
388 if (config1 & MIPS_CONF1_MD)
389 c->ases |= MIPS_ASE_MDMX;
390 if (config1 & MIPS_CONF1_WR)
391 c->options |= MIPS_CPU_WATCH;
392 if (config1 & MIPS_CONF1_CA)
393 c->ases |= MIPS_ASE_MIPS16;
394 if (config1 & MIPS_CONF1_EP)
395 c->options |= MIPS_CPU_EJTAG;
396 if (config1 & MIPS_CONF1_FP) {
397 c->options |= MIPS_CPU_FPU;
398 c->options |= MIPS_CPU_32FPR;
399 }
400 if (cpu_has_tlb)
401 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
402
403 return config1 & MIPS_CONF_M;
404}
405
406static inline unsigned int decode_config2(struct cpuinfo_mips *c)
407{
408 unsigned int config2;
409
410 config2 = read_c0_config2();
411
412 if (config2 & MIPS_CONF2_SL)
413 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
414
415 return config2 & MIPS_CONF_M;
416}
417
418static inline unsigned int decode_config3(struct cpuinfo_mips *c)
419{
420 unsigned int config3;
421
422 config3 = read_c0_config3();
423
424 if (config3 & MIPS_CONF3_SM)
425 c->ases |= MIPS_ASE_SMARTMIPS;
426 if (config3 & MIPS_CONF3_DSP)
427 c->ases |= MIPS_ASE_DSP;
428 if (config3 & MIPS_CONF3_VINT)
429 c->options |= MIPS_CPU_VINT;
430 if (config3 & MIPS_CONF3_VEIC)
431 c->options |= MIPS_CPU_VEIC;
432 if (config3 & MIPS_CONF3_MT)
433 c->ases |= MIPS_ASE_MIPSMT;
434 if (config3 & MIPS_CONF3_ULRI)
435 c->options |= MIPS_CPU_ULRI;
436
437 return config3 & MIPS_CONF_M;
438}
439
440static inline unsigned int decode_config4(struct cpuinfo_mips *c)
441{
442 unsigned int config4;
443
444 config4 = read_c0_config4();
445
446 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
447 && cpu_has_tlb)
448 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
449
450 c->kscratch_mask = (config4 >> 16) & 0xff;
451
452 return config4 & MIPS_CONF_M;
453}
454
455static void __cpuinit decode_configs(struct cpuinfo_mips *c)
456{
457 int ok;
458
459 /* MIPS32 or MIPS64 compliant CPU. */
460 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
461 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
462
463 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
464
465 ok = decode_config0(c); /* Read Config registers. */
466 BUG_ON(!ok); /* Arch spec violation! */
467 if (ok)
468 ok = decode_config1(c);
469 if (ok)
470 ok = decode_config2(c);
471 if (ok)
472 ok = decode_config3(c);
473 if (ok)
474 ok = decode_config4(c);
475
476 mips_probe_watch_registers(c);
477
478 if (cpu_has_mips_r2)
479 c->core = read_c0_ebase() & 0x3ff;
480}
481
333#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
334 | MIPS_CPU_COUNTER)
335
336static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
337{
338 switch (c->processor_id & 0xff00) {
339 case PRID_IMP_R2000:
340 c->cputype = CPU_R2000;

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633 }
634
635 c->isa_level = MIPS_CPU_ISA_III;
636 c->options = R4K_OPTS |
637 MIPS_CPU_FPU | MIPS_CPU_LLSC |
638 MIPS_CPU_32FPR;
639 c->tlbsize = 64;
640 break;
482#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
483 | MIPS_CPU_COUNTER)
484
485static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
486{
487 switch (c->processor_id & 0xff00) {
488 case PRID_IMP_R2000:
489 c->cputype = CPU_R2000;

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782 }
783
784 c->isa_level = MIPS_CPU_ISA_III;
785 c->options = R4K_OPTS |
786 MIPS_CPU_FPU | MIPS_CPU_LLSC |
787 MIPS_CPU_32FPR;
788 c->tlbsize = 64;
789 break;
641 }
642}
790 case PRID_IMP_LOONGSON1:
791 decode_configs(c);
643
792
644static char unknown_isa[] __cpuinitdata = KERN_ERR \
645 "Unsupported ISA type, c0.config0: %d.";
793 c->cputype = CPU_LOONGSON1;
646
794
647static inline unsigned int decode_config0(struct cpuinfo_mips *c)
648{
649 unsigned int config0;
650 int isa;
651
652 config0 = read_c0_config();
653
654 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
655 c->options |= MIPS_CPU_TLB;
656 isa = (config0 & MIPS_CONF_AT) >> 13;
657 switch (isa) {
658 case 0:
659 switch ((config0 & MIPS_CONF_AR) >> 10) {
660 case 0:
661 c->isa_level = MIPS_CPU_ISA_M32R1;
795 switch (c->processor_id & PRID_REV_MASK) {
796 case PRID_REV_LOONGSON1B:
797 __cpu_name[cpu] = "Loongson 1B";
662 break;
798 break;
663 case 1:
664 c->isa_level = MIPS_CPU_ISA_M32R2;
665 break;
666 default:
667 goto unknown;
668 }
799 }
800
669 break;
801 break;
670 case 2:
671 switch ((config0 & MIPS_CONF_AR) >> 10) {
672 case 0:
673 c->isa_level = MIPS_CPU_ISA_M64R1;
674 break;
675 case 1:
676 c->isa_level = MIPS_CPU_ISA_M64R2;
677 break;
678 default:
679 goto unknown;
680 }
681 break;
682 default:
683 goto unknown;
684 }
802 }
685
686 return config0 & MIPS_CONF_M;
687
688unknown:
689 panic(unknown_isa, config0);
690}
691
803}
804
692static inline unsigned int decode_config1(struct cpuinfo_mips *c)
693{
694 unsigned int config1;
695
696 config1 = read_c0_config1();
697
698 if (config1 & MIPS_CONF1_MD)
699 c->ases |= MIPS_ASE_MDMX;
700 if (config1 & MIPS_CONF1_WR)
701 c->options |= MIPS_CPU_WATCH;
702 if (config1 & MIPS_CONF1_CA)
703 c->ases |= MIPS_ASE_MIPS16;
704 if (config1 & MIPS_CONF1_EP)
705 c->options |= MIPS_CPU_EJTAG;
706 if (config1 & MIPS_CONF1_FP) {
707 c->options |= MIPS_CPU_FPU;
708 c->options |= MIPS_CPU_32FPR;
709 }
710 if (cpu_has_tlb)
711 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
712
713 return config1 & MIPS_CONF_M;
714}
715
716static inline unsigned int decode_config2(struct cpuinfo_mips *c)
717{
718 unsigned int config2;
719
720 config2 = read_c0_config2();
721
722 if (config2 & MIPS_CONF2_SL)
723 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
724
725 return config2 & MIPS_CONF_M;
726}
727
728static inline unsigned int decode_config3(struct cpuinfo_mips *c)
729{
730 unsigned int config3;
731
732 config3 = read_c0_config3();
733
734 if (config3 & MIPS_CONF3_SM)
735 c->ases |= MIPS_ASE_SMARTMIPS;
736 if (config3 & MIPS_CONF3_DSP)
737 c->ases |= MIPS_ASE_DSP;
738 if (config3 & MIPS_CONF3_VINT)
739 c->options |= MIPS_CPU_VINT;
740 if (config3 & MIPS_CONF3_VEIC)
741 c->options |= MIPS_CPU_VEIC;
742 if (config3 & MIPS_CONF3_MT)
743 c->ases |= MIPS_ASE_MIPSMT;
744 if (config3 & MIPS_CONF3_ULRI)
745 c->options |= MIPS_CPU_ULRI;
746
747 return config3 & MIPS_CONF_M;
748}
749
750static inline unsigned int decode_config4(struct cpuinfo_mips *c)
751{
752 unsigned int config4;
753
754 config4 = read_c0_config4();
755
756 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
757 && cpu_has_tlb)
758 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
759
760 c->kscratch_mask = (config4 >> 16) & 0xff;
761
762 return config4 & MIPS_CONF_M;
763}
764
765static void __cpuinit decode_configs(struct cpuinfo_mips *c)
766{
767 int ok;
768
769 /* MIPS32 or MIPS64 compliant CPU. */
770 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
771 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
772
773 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
774
775 ok = decode_config0(c); /* Read Config registers. */
776 BUG_ON(!ok); /* Arch spec violation! */
777 if (ok)
778 ok = decode_config1(c);
779 if (ok)
780 ok = decode_config2(c);
781 if (ok)
782 ok = decode_config3(c);
783 if (ok)
784 ok = decode_config4(c);
785
786 mips_probe_watch_registers(c);
787
788 if (cpu_has_mips_r2)
789 c->core = read_c0_ebase() & 0x3ff;
790}
791
792static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
793{
794 decode_configs(c);
795 switch (c->processor_id & 0xff00) {
796 case PRID_IMP_4KC:
797 c->cputype = CPU_4KC;
798 __cpu_name[cpu] = "MIPS 4Kc";
799 break;

--- 398 unchanged lines hidden --- 		805static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
806{
807 decode_configs(c);
808 switch (c->processor_id & 0xff00) {
809 case PRID_IMP_4KC:
810 c->cputype = CPU_4KC;
811 __cpu_name[cpu] = "MIPS 4Kc";
812 break;

--- 398 unchanged lines hidden ---