spinlock.h (fb3a6bbc912b12347614e5742c7c61416cdb0ca0) spinlock.h (e5931943d02bf751b1ec849c0d2ade23d76a8d41)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */

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243 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
244 * read-locks.
245 */
246
247/*
248 * read_can_lock - would read_trylock() succeed?
249 * @lock: the rwlock in question.
250 */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */

--- 234 unchanged lines hidden (view full) ---

243 * needs to get a irq-safe write-lock, but readers can get non-irqsafe
244 * read-locks.
245 */
246
247/*
248 * read_can_lock - would read_trylock() succeed?
249 * @lock: the rwlock in question.
250 */
251#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
251#define arch_read_can_lock(rw) ((rw)->lock >= 0)
252
253/*
254 * write_can_lock - would write_trylock() succeed?
255 * @lock: the rwlock in question.
256 */
252
253/*
254 * write_can_lock - would write_trylock() succeed?
255 * @lock: the rwlock in question.
256 */
257#define __raw_write_can_lock(rw) (!(rw)->lock)
257#define arch_write_can_lock(rw) (!(rw)->lock)
258
258
259static inline void __raw_read_lock(arch_rwlock_t *rw)
259static inline void arch_read_lock(arch_rwlock_t *rw)
260{
261 unsigned int tmp;
262
263 if (R10000_LLSC_WAR) {
264 __asm__ __volatile__(
260{
261 unsigned int tmp;
262
263 if (R10000_LLSC_WAR) {
264 __asm__ __volatile__(
265 " .set noreorder # __raw_read_lock \n"
265 " .set noreorder # arch_read_lock \n"
266 "1: ll %1, %2 \n"
267 " bltz %1, 1b \n"
268 " addu %1, 1 \n"
269 " sc %1, %0 \n"
270 " beqzl %1, 1b \n"
271 " nop \n"
272 " .set reorder \n"
273 : "=m" (rw->lock), "=&r" (tmp)
274 : "m" (rw->lock)
275 : "memory");
276 } else {
277 __asm__ __volatile__(
266 "1: ll %1, %2 \n"
267 " bltz %1, 1b \n"
268 " addu %1, 1 \n"
269 " sc %1, %0 \n"
270 " beqzl %1, 1b \n"
271 " nop \n"
272 " .set reorder \n"
273 : "=m" (rw->lock), "=&r" (tmp)
274 : "m" (rw->lock)
275 : "memory");
276 } else {
277 __asm__ __volatile__(
278 " .set noreorder # __raw_read_lock \n"
278 " .set noreorder # arch_read_lock \n"
279 "1: ll %1, %2 \n"
280 " bltz %1, 2f \n"
281 " addu %1, 1 \n"
282 " sc %1, %0 \n"
283 " beqz %1, 1b \n"
284 " nop \n"
285 " .subsection 2 \n"
286 "2: ll %1, %2 \n"

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296 }
297
298 smp_llsc_mb();
299}
300
301/* Note the use of sub, not subu which will make the kernel die with an
302 overflow exception if we ever try to unlock an rwlock that is already
303 unlocked or is being held by a writer. */
279 "1: ll %1, %2 \n"
280 " bltz %1, 2f \n"
281 " addu %1, 1 \n"
282 " sc %1, %0 \n"
283 " beqz %1, 1b \n"
284 " nop \n"
285 " .subsection 2 \n"
286 "2: ll %1, %2 \n"

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296 }
297
298 smp_llsc_mb();
299}
300
301/* Note the use of sub, not subu which will make the kernel die with an
302 overflow exception if we ever try to unlock an rwlock that is already
303 unlocked or is being held by a writer. */
304static inline void __raw_read_unlock(arch_rwlock_t *rw)
304static inline void arch_read_unlock(arch_rwlock_t *rw)
305{
306 unsigned int tmp;
307
308 smp_llsc_mb();
309
310 if (R10000_LLSC_WAR) {
311 __asm__ __volatile__(
305{
306 unsigned int tmp;
307
308 smp_llsc_mb();
309
310 if (R10000_LLSC_WAR) {
311 __asm__ __volatile__(
312 "1: ll %1, %2 # __raw_read_unlock \n"
312 "1: ll %1, %2 # arch_read_unlock \n"
313 " sub %1, 1 \n"
314 " sc %1, %0 \n"
315 " beqzl %1, 1b \n"
316 : "=m" (rw->lock), "=&r" (tmp)
317 : "m" (rw->lock)
318 : "memory");
319 } else {
320 __asm__ __volatile__(
313 " sub %1, 1 \n"
314 " sc %1, %0 \n"
315 " beqzl %1, 1b \n"
316 : "=m" (rw->lock), "=&r" (tmp)
317 : "m" (rw->lock)
318 : "memory");
319 } else {
320 __asm__ __volatile__(
321 " .set noreorder # __raw_read_unlock \n"
321 " .set noreorder # arch_read_unlock \n"
322 "1: ll %1, %2 \n"
323 " sub %1, 1 \n"
324 " sc %1, %0 \n"
325 " beqz %1, 2f \n"
326 " nop \n"
327 " .subsection 2 \n"
328 "2: b 1b \n"
329 " nop \n"
330 " .previous \n"
331 " .set reorder \n"
332 : "=m" (rw->lock), "=&r" (tmp)
333 : "m" (rw->lock)
334 : "memory");
335 }
336}
337
322 "1: ll %1, %2 \n"
323 " sub %1, 1 \n"
324 " sc %1, %0 \n"
325 " beqz %1, 2f \n"
326 " nop \n"
327 " .subsection 2 \n"
328 "2: b 1b \n"
329 " nop \n"
330 " .previous \n"
331 " .set reorder \n"
332 : "=m" (rw->lock), "=&r" (tmp)
333 : "m" (rw->lock)
334 : "memory");
335 }
336}
337
338static inline void __raw_write_lock(arch_rwlock_t *rw)
338static inline void arch_write_lock(arch_rwlock_t *rw)
339{
340 unsigned int tmp;
341
342 if (R10000_LLSC_WAR) {
343 __asm__ __volatile__(
339{
340 unsigned int tmp;
341
342 if (R10000_LLSC_WAR) {
343 __asm__ __volatile__(
344 " .set noreorder # __raw_write_lock \n"
344 " .set noreorder # arch_write_lock \n"
345 "1: ll %1, %2 \n"
346 " bnez %1, 1b \n"
347 " lui %1, 0x8000 \n"
348 " sc %1, %0 \n"
349 " beqzl %1, 1b \n"
350 " nop \n"
351 " .set reorder \n"
352 : "=m" (rw->lock), "=&r" (tmp)
353 : "m" (rw->lock)
354 : "memory");
355 } else {
356 __asm__ __volatile__(
345 "1: ll %1, %2 \n"
346 " bnez %1, 1b \n"
347 " lui %1, 0x8000 \n"
348 " sc %1, %0 \n"
349 " beqzl %1, 1b \n"
350 " nop \n"
351 " .set reorder \n"
352 : "=m" (rw->lock), "=&r" (tmp)
353 : "m" (rw->lock)
354 : "memory");
355 } else {
356 __asm__ __volatile__(
357 " .set noreorder # __raw_write_lock \n"
357 " .set noreorder # arch_write_lock \n"
358 "1: ll %1, %2 \n"
359 " bnez %1, 2f \n"
360 " lui %1, 0x8000 \n"
361 " sc %1, %0 \n"
362 " beqz %1, 2f \n"
363 " nop \n"
364 " .subsection 2 \n"
365 "2: ll %1, %2 \n"

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372 : "=m" (rw->lock), "=&r" (tmp)
373 : "m" (rw->lock)
374 : "memory");
375 }
376
377 smp_llsc_mb();
378}
379
358 "1: ll %1, %2 \n"
359 " bnez %1, 2f \n"
360 " lui %1, 0x8000 \n"
361 " sc %1, %0 \n"
362 " beqz %1, 2f \n"
363 " nop \n"
364 " .subsection 2 \n"
365 "2: ll %1, %2 \n"

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372 : "=m" (rw->lock), "=&r" (tmp)
373 : "m" (rw->lock)
374 : "memory");
375 }
376
377 smp_llsc_mb();
378}
379
380static inline void __raw_write_unlock(arch_rwlock_t *rw)
380static inline void arch_write_unlock(arch_rwlock_t *rw)
381{
382 smp_mb();
383
384 __asm__ __volatile__(
381{
382 smp_mb();
383
384 __asm__ __volatile__(
385 " # __raw_write_unlock \n"
385 " # arch_write_unlock \n"
386 " sw $0, %0 \n"
387 : "=m" (rw->lock)
388 : "m" (rw->lock)
389 : "memory");
390}
391
386 " sw $0, %0 \n"
387 : "=m" (rw->lock)
388 : "m" (rw->lock)
389 : "memory");
390}
391
392static inline int __raw_read_trylock(arch_rwlock_t *rw)
392static inline int arch_read_trylock(arch_rwlock_t *rw)
393{
394 unsigned int tmp;
395 int ret;
396
397 if (R10000_LLSC_WAR) {
398 __asm__ __volatile__(
393{
394 unsigned int tmp;
395 int ret;
396
397 if (R10000_LLSC_WAR) {
398 __asm__ __volatile__(
399 " .set noreorder # __raw_read_trylock \n"
399 " .set noreorder # arch_read_trylock \n"
400 " li %2, 0 \n"
401 "1: ll %1, %3 \n"
402 " bltz %1, 2f \n"
403 " addu %1, 1 \n"
404 " sc %1, %0 \n"
405 " .set reorder \n"
406 " beqzl %1, 1b \n"
407 " nop \n"
408 __WEAK_LLSC_MB
409 " li %2, 1 \n"
410 "2: \n"
411 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
412 : "m" (rw->lock)
413 : "memory");
414 } else {
415 __asm__ __volatile__(
400 " li %2, 0 \n"
401 "1: ll %1, %3 \n"
402 " bltz %1, 2f \n"
403 " addu %1, 1 \n"
404 " sc %1, %0 \n"
405 " .set reorder \n"
406 " beqzl %1, 1b \n"
407 " nop \n"
408 __WEAK_LLSC_MB
409 " li %2, 1 \n"
410 "2: \n"
411 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
412 : "m" (rw->lock)
413 : "memory");
414 } else {
415 __asm__ __volatile__(
416 " .set noreorder # __raw_read_trylock \n"
416 " .set noreorder # arch_read_trylock \n"
417 " li %2, 0 \n"
418 "1: ll %1, %3 \n"
419 " bltz %1, 2f \n"
420 " addu %1, 1 \n"
421 " sc %1, %0 \n"
422 " beqz %1, 1b \n"
423 " nop \n"
424 " .set reorder \n"
425 __WEAK_LLSC_MB
426 " li %2, 1 \n"
427 "2: \n"
428 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
429 : "m" (rw->lock)
430 : "memory");
431 }
432
433 return ret;
434}
435
417 " li %2, 0 \n"
418 "1: ll %1, %3 \n"
419 " bltz %1, 2f \n"
420 " addu %1, 1 \n"
421 " sc %1, %0 \n"
422 " beqz %1, 1b \n"
423 " nop \n"
424 " .set reorder \n"
425 __WEAK_LLSC_MB
426 " li %2, 1 \n"
427 "2: \n"
428 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
429 : "m" (rw->lock)
430 : "memory");
431 }
432
433 return ret;
434}
435
436static inline int __raw_write_trylock(arch_rwlock_t *rw)
436static inline int arch_write_trylock(arch_rwlock_t *rw)
437{
438 unsigned int tmp;
439 int ret;
440
441 if (R10000_LLSC_WAR) {
442 __asm__ __volatile__(
437{
438 unsigned int tmp;
439 int ret;
440
441 if (R10000_LLSC_WAR) {
442 __asm__ __volatile__(
443 " .set noreorder # __raw_write_trylock \n"
443 " .set noreorder # arch_write_trylock \n"
444 " li %2, 0 \n"
445 "1: ll %1, %3 \n"
446 " bnez %1, 2f \n"
447 " lui %1, 0x8000 \n"
448 " sc %1, %0 \n"
449 " beqzl %1, 1b \n"
450 " nop \n"
451 __WEAK_LLSC_MB
452 " li %2, 1 \n"
453 " .set reorder \n"
454 "2: \n"
455 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
456 : "m" (rw->lock)
457 : "memory");
458 } else {
459 __asm__ __volatile__(
444 " li %2, 0 \n"
445 "1: ll %1, %3 \n"
446 " bnez %1, 2f \n"
447 " lui %1, 0x8000 \n"
448 " sc %1, %0 \n"
449 " beqzl %1, 1b \n"
450 " nop \n"
451 __WEAK_LLSC_MB
452 " li %2, 1 \n"
453 " .set reorder \n"
454 "2: \n"
455 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
456 : "m" (rw->lock)
457 : "memory");
458 } else {
459 __asm__ __volatile__(
460 " .set noreorder # __raw_write_trylock \n"
460 " .set noreorder # arch_write_trylock \n"
461 " li %2, 0 \n"
462 "1: ll %1, %3 \n"
463 " bnez %1, 2f \n"
464 " lui %1, 0x8000 \n"
465 " sc %1, %0 \n"
466 " beqz %1, 3f \n"
467 " li %2, 1 \n"
468 "2: \n"

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475 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
476 : "m" (rw->lock)
477 : "memory");
478 }
479
480 return ret;
481}
482
461 " li %2, 0 \n"
462 "1: ll %1, %3 \n"
463 " bnez %1, 2f \n"
464 " lui %1, 0x8000 \n"
465 " sc %1, %0 \n"
466 " beqz %1, 3f \n"
467 " li %2, 1 \n"
468 "2: \n"

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475 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
476 : "m" (rw->lock)
477 : "memory");
478 }
479
480 return ret;
481}
482
483#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
484#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
483#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
484#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
485
486#define arch_spin_relax(lock) cpu_relax()
487#define arch_read_relax(lock) cpu_relax()
488#define arch_write_relax(lock) cpu_relax()
489
490#endif /* _ASM_SPINLOCK_H */
485
486#define arch_spin_relax(lock) cpu_relax()
487#define arch_read_relax(lock) cpu_relax()
488#define arch_write_relax(lock) cpu_relax()
489
490#endif /* _ASM_SPINLOCK_H */