cpu.h (f2e5d078f7f02d4289db31f5f63e23e39914075e) cpu.h (f8fa4811dbb264aef13f982e963389fd828b1ac0)
1/*
2 * cpu.h: Values of the PRId register used to match up
3 * various MIPS cpu types.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 2004 Maciej W. Rozycki
7 */
8#ifndef _ASM_CPU_H

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91#define PRID_IMP_4KSD 0x9200
92#define PRID_IMP_24K 0x9300
93#define PRID_IMP_34K 0x9500
94#define PRID_IMP_24KE 0x9600
95#define PRID_IMP_74K 0x9700
96#define PRID_IMP_1004K 0x9900
97#define PRID_IMP_1074K 0x9a00
98#define PRID_IMP_M14KC 0x9c00
1/*
2 * cpu.h: Values of the PRId register used to match up
3 * various MIPS cpu types.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 2004 Maciej W. Rozycki
7 */
8#ifndef _ASM_CPU_H

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91#define PRID_IMP_4KSD 0x9200
92#define PRID_IMP_24K 0x9300
93#define PRID_IMP_34K 0x9500
94#define PRID_IMP_24KE 0x9600
95#define PRID_IMP_74K 0x9700
96#define PRID_IMP_1004K 0x9900
97#define PRID_IMP_1074K 0x9a00
98#define PRID_IMP_M14KC 0x9c00
99#define PRID_IMP_M14KEC 0x9e00
99
100/*
101 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
102 */
103
104#define PRID_IMP_SB1 0x0100
105#define PRID_IMP_SB1A 0x1100
106

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259 CPU_TX3912, CPU_TX3922, CPU_TX3927,
260
261 /*
262 * MIPS32 class processors
263 */
264 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
265 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
266 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
100
101/*
102 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
103 */
104
105#define PRID_IMP_SB1 0x0100
106#define PRID_IMP_SB1A 0x1100
107

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260 CPU_TX3912, CPU_TX3922, CPU_TX3927,
261
262 /*
263 * MIPS32 class processors
264 */
265 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
266 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
267 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
268 CPU_M14KEC,
267
268 /*
269 * MIPS64 class processors
270 */
271 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
272 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
273 CPU_XLR, CPU_XLP,
274

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317#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
318#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
319#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
320#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
321#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
322#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
323#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
324#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
269
270 /*
271 * MIPS64 class processors
272 */
273 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
274 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
275 CPU_XLR, CPU_XLP,
276

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319#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
320#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
321#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
322#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
323#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
324#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
325#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
326#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
327#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
325
326/*
327 * CPU ASE encodings
328 */
329#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
330#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
331#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
332#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
333#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
334#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
335#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
336
337
338#endif /* _ASM_CPU_H */
328
329/*
330 * CPU ASE encodings
331 */
332#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
333#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
334#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
335#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
336#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
337#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
338#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
339
340
341#endif /* _ASM_CPU_H */