| cpu.h (d75e2c9ad97c40f6d2cdaf2e16381b2034d19a6f) | cpu.h (2fa36399e63c911134f28b6878aada9b395c4209) |
|---|---|
| 1/* 2 * cpu.h: Values of the PRId register used to match up 3 * various MIPS cpu types. 4 * 5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 6 * Copyright (C) 2004 Maciej W. Rozycki 7 */ 8#ifndef _ASM_CPU_H --- 183 unchanged lines hidden (view full) --- 192#define PRID_REV_TX3927 0x0040 193#define PRID_REV_VR4111 0x0050 194#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 195#define PRID_REV_VR4121 0x0060 196#define PRID_REV_VR4122 0x0070 197#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 198#define PRID_REV_VR4130 0x0080 199#define PRID_REV_34K_V1_0_2 0x0022 | 1/* 2 * cpu.h: Values of the PRId register used to match up 3 * various MIPS cpu types. 4 * 5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 6 * Copyright (C) 2004 Maciej W. Rozycki 7 */ 8#ifndef _ASM_CPU_H --- 183 unchanged lines hidden (view full) --- 192#define PRID_REV_TX3927 0x0040 193#define PRID_REV_VR4111 0x0050 194#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 195#define PRID_REV_VR4121 0x0060 196#define PRID_REV_VR4122 0x0070 197#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 198#define PRID_REV_VR4130 0x0080 199#define PRID_REV_34K_V1_0_2 0x0022 |
| 200#define PRID_REV_LOONGSON1B 0x0020 |
|
| 200#define PRID_REV_LOONGSON2E 0x0002 201#define PRID_REV_LOONGSON2F 0x0003 202 203/* 204 * Older processors used to encode processor version and revision in two 205 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 206 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 207 * the patch number. *ARGH* --- 48 unchanged lines hidden (view full) --- 256 */ 257 CPU_TX3912, CPU_TX3922, CPU_TX3927, 258 259 /* 260 * MIPS32 class processors 261 */ 262 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 263 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, | 201#define PRID_REV_LOONGSON2E 0x0002 202#define PRID_REV_LOONGSON2F 0x0003 203 204/* 205 * Older processors used to encode processor version and revision in two 206 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 207 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 208 * the patch number. *ARGH* --- 48 unchanged lines hidden (view full) --- 257 */ 258 CPU_TX3912, CPU_TX3922, CPU_TX3927, 259 260 /* 261 * MIPS32 class processors 262 */ 263 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 264 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, |
| 264 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC, | 265 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, |
| 265 266 /* 267 * MIPS64 class processors 268 */ 269 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 270 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 271 CPU_XLR, CPU_XLP, 272 --- 61 unchanged lines hidden --- | 266 267 /* 268 * MIPS64 class processors 269 */ 270 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 271 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 272 CPU_XLR, CPU_XLP, 273 --- 61 unchanged lines hidden --- |