ocelot.dtsi (3eb66e91a25497065c5322b1268cbc3953642227) ocelot.dtsi (b596229448dd2a263cdc4906e60b1b2249777ee4)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/ {
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
8

--- 118 unchanged lines hidden (view full) ---

127 <0x1220000 0x100>,
128 <0x1230000 0x100>,
129 <0x1240000 0x100>,
130 <0x1250000 0x100>,
131 <0x1260000 0x100>,
132 <0x1270000 0x100>,
133 <0x1280000 0x100>,
134 <0x1800000 0x80000>,
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/ {
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
8

--- 118 unchanged lines hidden (view full) ---

127 <0x1220000 0x100>,
128 <0x1230000 0x100>,
129 <0x1240000 0x100>,
130 <0x1250000 0x100>,
131 <0x1260000 0x100>,
132 <0x1270000 0x100>,
133 <0x1280000 0x100>,
134 <0x1800000 0x80000>,
135 <0x1880000 0x10000>;
135 <0x1880000 0x10000>,
136 <0x1060000 0x10000>;
136 reg-names = "sys", "rew", "qs", "port0", "port1",
137 "port2", "port3", "port4", "port5", "port6",
138 "port7", "port8", "port9", "port10", "qsys",
137 reg-names = "sys", "rew", "qs", "port0", "port1",
138 "port2", "port3", "port4", "port5", "port6",
139 "port7", "port8", "port9", "port10", "qsys",
139 "ana";
140 "ana", "s2";
140 interrupts = <21 22>;
141 interrupt-names = "xtr", "inj";
142
143 ethernet-ports {
144 #address-cells = <1>;
145 #size-cells = <0>;
146
147 port0: port@0 {

--- 116 unchanged lines hidden --- 		141 interrupts = <21 22>;
142 interrupt-names = "xtr", "inj";
143
144 ethernet-ports {
145 #address-cells = <1>;
146 #size-cells = <0>;
147
148 port0: port@0 {

--- 116 unchanged lines hidden ---