cpu.c (ec68c5206ab32f67583c1297f7883ceb91b043eb) cpu.c (04712f3ff6e3a42ef658b55b0f99478f4f0682e3)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */

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58 __GEN_CPU_REGS_TABLE(6358)
59};
60
61static const int bcm6358_irqs[] = {
62 __GEN_CPU_IRQ_TABLE(6358)
63
64};
65
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */

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58 __GEN_CPU_REGS_TABLE(6358)
59};
60
61static const int bcm6358_irqs[] = {
62 __GEN_CPU_IRQ_TABLE(6358)
63
64};
65
66static const unsigned long bcm6368_regs_base[] = {
67 __GEN_CPU_REGS_TABLE(6368)
68};
69
70static const int bcm6368_irqs[] = {
71 __GEN_CPU_IRQ_TABLE(6368)
72
73};
74
66u16 __bcm63xx_get_cpu_id(void)
67{
68 return bcm63xx_cpu_id;
69}
70
71EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
72
73u16 bcm63xx_get_cpu_rev(void)

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84
85unsigned int bcm63xx_get_memory_size(void)
86{
87 return bcm63xx_memory_size;
88}
89
90static unsigned int detect_cpu_clock(void)
91{
75u16 __bcm63xx_get_cpu_id(void)
76{
77 return bcm63xx_cpu_id;
78}
79
80EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
81
82u16 bcm63xx_get_cpu_rev(void)

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93
94unsigned int bcm63xx_get_memory_size(void)
95{
96 return bcm63xx_memory_size;
97}
98
99static unsigned int detect_cpu_clock(void)
100{
92 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
93
94 /* BCM6338 has a fixed 240 Mhz frequency */
95 if (BCMCPU_IS_6338())
101 switch (bcm63xx_get_cpu_id()) {
102 case BCM6338_CPU_ID:
103 /* BCM6338 has a fixed 240 Mhz frequency */
96 return 240000000;
97
104 return 240000000;
105
98 /* BCM6345 has a fixed 140Mhz frequency */
99 if (BCMCPU_IS_6345())
106 case BCM6345_CPU_ID:
107 /* BCM6345 has a fixed 140Mhz frequency */
100 return 140000000;
101
108 return 140000000;
109
102 /*
103 * frequency depends on PLL configuration:
104 */
105 if (BCMCPU_IS_6348()) {
110 case BCM6348_CPU_ID:
111 {
112 unsigned int tmp, n1, n2, m1;
113
106 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
107 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
108 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
109 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
110 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
111 n1 += 1;
112 n2 += 2;
113 m1 += 1;
114 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
115 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
116 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
117 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
118 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
119 n1 += 1;
120 n2 += 2;
121 m1 += 1;
122 return (16 * 1000000 * n1 * n2) / m1;
114 }
115
123 }
124
116 if (BCMCPU_IS_6358()) {
125 case BCM6358_CPU_ID:
126 {
127 unsigned int tmp, n1, n2, m1;
128
117 /* 16MHz * N1 * N2 / M1_CPU */
118 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
119 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
120 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
121 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
129 /* 16MHz * N1 * N2 / M1_CPU */
130 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
131 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
132 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
133 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
134 return (16 * 1000000 * n1 * n2) / m1;
122 }
123
135 }
136
124 return (16 * 1000000 * n1 * n2) / m1;
137 case BCM6368_CPU_ID:
138 {
139 unsigned int tmp, p1, p2, ndiv, m1;
140
141 /* (64MHz / P1) * P2 * NDIV / M1_CPU */
142 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
143
144 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
145 DMIPSPLLCFG_6368_P1_SHIFT;
146
147 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
148 DMIPSPLLCFG_6368_P2_SHIFT;
149
150 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
151 DMIPSPLLCFG_6368_NDIV_SHIFT;
152
153 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
154 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
155 DMIPSPLLDIV_6368_MDIV_SHIFT;
156
157 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
158 }
159
160 default:
161 BUG();
162 }
125}
126
127/*
128 * attempt to detect the amount of memory installed
129 */
130static unsigned int detect_memory_size(void)
131{
132 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;

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138 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
139 val = bcm_sdram_readl(SDRAM_CFG_REG);
140 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
141 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
142 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
143 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
144 }
145
163}
164
165/*
166 * attempt to detect the amount of memory installed
167 */
168static unsigned int detect_memory_size(void)
169{
170 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;

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176 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
177 val = bcm_sdram_readl(SDRAM_CFG_REG);
178 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
179 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
180 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
181 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
182 }
183
146 if (BCMCPU_IS_6358()) {
184 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
147 val = bcm_memc_readl(MEMC_CFG_REG);
148 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
149 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
150 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
151 banks = 2;
152 }
153
154 /* 0 => 11 address bits ... 2 => 13 address bits */

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183 }
184 break;
185 case CPU_BMIPS32:
186 expected_cpu_id = BCM6345_CPU_ID;
187 bcm63xx_regs_base = bcm6345_regs_base;
188 bcm63xx_irqs = bcm6345_irqs;
189 break;
190 case CPU_BMIPS4350:
185 val = bcm_memc_readl(MEMC_CFG_REG);
186 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
187 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
188 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
189 banks = 2;
190 }
191
192 /* 0 => 11 address bits ... 2 => 13 address bits */

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221 }
222 break;
223 case CPU_BMIPS32:
224 expected_cpu_id = BCM6345_CPU_ID;
225 bcm63xx_regs_base = bcm6345_regs_base;
226 bcm63xx_irqs = bcm6345_irqs;
227 break;
228 case CPU_BMIPS4350:
191 expected_cpu_id = BCM6358_CPU_ID;
192 bcm63xx_regs_base = bcm6358_regs_base;
193 bcm63xx_irqs = bcm6358_irqs;
229 switch (read_c0_prid() & 0xf0) {
230 case 0x10:
231 expected_cpu_id = BCM6358_CPU_ID;
232 bcm63xx_regs_base = bcm6358_regs_base;
233 bcm63xx_irqs = bcm6358_irqs;
234 break;
235 case 0x30:
236 expected_cpu_id = BCM6368_CPU_ID;
237 bcm63xx_regs_base = bcm6368_regs_base;
238 bcm63xx_irqs = bcm6368_irqs;
239 break;
240 }
194 break;
195 }
196
197 /*
198 * really early to panic, but delaying panic would not help since we
199 * will never get any working console
200 */
201 if (!expected_cpu_id)

--- 24 unchanged lines hidden --- 		241 break;
242 }
243
244 /*
245 * really early to panic, but delaying panic would not help since we
246 * will never get any working console
247 */
248 if (!expected_cpu_id)

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