clk.c (f2d1035e956052d29c83fe8f8da0d056af6d221a) clk.c (ba00e2e5c24f447fb09437a99df697787103f0cd)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/module.h>
10#include <linux/mutex.h>
11#include <linux/err.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <bcm63xx_cpu.h>
15#include <bcm63xx_io.h>
16#include <bcm63xx_regs.h>
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/module.h>
10#include <linux/mutex.h>
11#include <linux/err.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <bcm63xx_cpu.h>
15#include <bcm63xx_io.h>
16#include <bcm63xx_regs.h>
17#include <bcm63xx_reset.h>
17#include <bcm63xx_clk.h>
18
19static DEFINE_MUTEX(clocks_mutex);
20
21
22static void clk_enable_unlocked(struct clk *clk)
23{
24 if (clk->set && (clk->usage++) == 0)

--- 94 unchanged lines hidden (view full) ---

119static void enetsw_set(struct clk *clk, int enable)
120{
121 if (!BCMCPU_IS_6368())
122 return;
123 bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
124 CKCTL_6368_SWPKT_USB_EN |
125 CKCTL_6368_SWPKT_SAR_EN, enable);
126 if (enable) {
18#include <bcm63xx_clk.h>
19
20static DEFINE_MUTEX(clocks_mutex);
21
22
23static void clk_enable_unlocked(struct clk *clk)
24{
25 if (clk->set && (clk->usage++) == 0)

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120static void enetsw_set(struct clk *clk, int enable)
121{
122 if (!BCMCPU_IS_6368())
123 return;
124 bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
125 CKCTL_6368_SWPKT_USB_EN |
126 CKCTL_6368_SWPKT_SAR_EN, enable);
127 if (enable) {
127 u32 val;
128
129 /* reset switch core afer clock change */
128 /* reset switch core afer clock change */
130 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
131 val &= ~SOFTRESET_6368_ENETSW_MASK;
132 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
129 bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
133 msleep(10);
130 msleep(10);
134 val |= SOFTRESET_6368_ENETSW_MASK;
135 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
131 bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
136 msleep(10);
137 }
138}
139
140static struct clk clk_enetsw = {
141 .set = enetsw_set,
142};
143

--- 73 unchanged lines hidden (view full) ---

217{
218 if (!BCMCPU_IS_6368())
219 return;
220
221 bcm_hwclock_set(CKCTL_6368_SAR_EN |
222 CKCTL_6368_SWPKT_SAR_EN, enable);
223
224 if (enable) {
132 msleep(10);
133 }
134}
135
136static struct clk clk_enetsw = {
137 .set = enetsw_set,
138};
139

--- 73 unchanged lines hidden (view full) ---

213{
214 if (!BCMCPU_IS_6368())
215 return;
216
217 bcm_hwclock_set(CKCTL_6368_SAR_EN |
218 CKCTL_6368_SWPKT_SAR_EN, enable);
219
220 if (enable) {
225 u32 val;
226
227 /* reset sar core afer clock change */
221 /* reset sar core afer clock change */
228 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
229 val &= ~SOFTRESET_6368_SAR_MASK;
230 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
222 bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
231 mdelay(1);
223 mdelay(1);
232 val |= SOFTRESET_6368_SAR_MASK;
233 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
224 bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
234 mdelay(1);
235 }
236}
237
238
239static struct clk clk_xtm = {
240 .set = xtm_set,
241};

--- 99 unchanged lines hidden --- 		225 mdelay(1);
226 }
227}
228
229
230static struct clk clk_xtm = {
231 .set = xtm_set,
232};

--- 99 unchanged lines hidden ---