cacheflush.h (f790c0ca6fad60b544bb73eda8cc841a6436725b) cacheflush.h (79e87830faf22ca636b1a1d8f4deb430ea6e1c8b)
1/*
2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
4 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
5 * based on v850 version which was
6 * Copyright (C) 2001,02,03 NEC Electronics Corporation
7 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file COPYING in the main directory of this
11 * archive for more details.
12 *
13 */
14
15#ifndef _ASM_MICROBLAZE_CACHEFLUSH_H
16#define _ASM_MICROBLAZE_CACHEFLUSH_H
17
18/* Somebody depends on this; sigh... */
19#include <linux/mm.h>
1/*
2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
4 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
5 * based on v850 version which was
6 * Copyright (C) 2001,02,03 NEC Electronics Corporation
7 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file COPYING in the main directory of this
11 * archive for more details.
12 *
13 */
14
15#ifndef _ASM_MICROBLAZE_CACHEFLUSH_H
16#define _ASM_MICROBLAZE_CACHEFLUSH_H
17
18/* Somebody depends on this; sigh... */
19#include <linux/mm.h>
20#include <linux/io.h>
20
21/* Look at Documentation/cachetlb.txt */
22
23/*
24 * Cache handling functions.
25 * Microblaze has a write-through data cache, meaning that the data cache
26 * never needs to be flushed. The only flushing operations that are
27 * implemented are to invalidate the instruction cache. These are called

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55
56#define enable_icache() mbc->ie();
57#define disable_icache() mbc->id();
58#define flush_icache() mbc->ifl();
59#define flush_icache_range(start, end) mbc->iflr(start, end);
60#define invalidate_icache() mbc->iin();
61#define invalidate_icache_range(start, end) mbc->iinr(start, end);
62
21
22/* Look at Documentation/cachetlb.txt */
23
24/*
25 * Cache handling functions.
26 * Microblaze has a write-through data cache, meaning that the data cache
27 * never needs to be flushed. The only flushing operations that are
28 * implemented are to invalidate the instruction cache. These are called

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56
57#define enable_icache() mbc->ie();
58#define disable_icache() mbc->id();
59#define flush_icache() mbc->ifl();
60#define flush_icache_range(start, end) mbc->iflr(start, end);
61#define invalidate_icache() mbc->iin();
62#define invalidate_icache_range(start, end) mbc->iinr(start, end);
63
63
64#define flush_icache_user_range(vma, pg, adr, len) flush_icache();
65#define flush_icache_page(vma, pg) do { } while (0)
66
67#define enable_dcache() mbc->de();
68#define disable_dcache() mbc->dd();
69/* FIXME for LL-temac driver */
70#define invalidate_dcache() mbc->din();
71#define invalidate_dcache_range(start, end) mbc->dinr(start, end);
72#define flush_dcache() mbc->dfl();
73#define flush_dcache_range(start, end) mbc->dflr(start, end);
74
64#define flush_icache_user_range(vma, pg, adr, len) flush_icache();
65#define flush_icache_page(vma, pg) do { } while (0)
66
67#define enable_dcache() mbc->de();
68#define disable_dcache() mbc->dd();
69/* FIXME for LL-temac driver */
70#define invalidate_dcache() mbc->din();
71#define invalidate_dcache_range(start, end) mbc->dinr(start, end);
72#define flush_dcache() mbc->dfl();
73#define flush_dcache_range(start, end) mbc->dflr(start, end);
74
75#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
76/* D-cache aliasing problem can't happen - cache is between MMU and ram */
77#define flush_dcache_page(page) do { } while (0)
75#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
76/* MS: We have to implement it because of rootfs-jffs2 issue on WB */
77#define flush_dcache_page(page) \
78do { \
79 unsigned long addr = (unsigned long) page_address(page); /* virtual */ \
80 addr = (u32)virt_to_phys((void *)addr); \
81 flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \
82} while (0);
83
78#define flush_dcache_mmap_lock(mapping) do { } while (0)
79#define flush_dcache_mmap_unlock(mapping) do { } while (0)
80
81
82#define flush_cache_dup_mm(mm) do { } while (0)
83#define flush_cache_vmap(start, end) do { } while (0)
84#define flush_cache_vunmap(start, end) do { } while (0)
85#define flush_cache_mm(mm) do { } while (0)

--- 24 unchanged lines hidden --- 		84#define flush_dcache_mmap_lock(mapping) do { } while (0)
85#define flush_dcache_mmap_unlock(mapping) do { } while (0)
86
87
88#define flush_cache_dup_mm(mm) do { } while (0)
89#define flush_cache_vmap(start, end) do { } while (0)
90#define flush_cache_vunmap(start, end) do { } while (0)
91#define flush_cache_mm(mm) do { } while (0)

--- 24 unchanged lines hidden ---