spinlock.h (fb3a6bbc912b12347614e5742c7c61416cdb0ca0) spinlock.h (e5931943d02bf751b1ec849c0d2ade23d76a8d41)
1#ifndef _ASM_IA64_SPINLOCK_H
2#define _ASM_IA64_SPINLOCK_H
3
4/*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
8 *

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135 arch_spin_lock(lock);
136}
137
138static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
139{
140 __ticket_spin_unlock_wait(lock);
141}
142
1#ifndef _ASM_IA64_SPINLOCK_H
2#define _ASM_IA64_SPINLOCK_H
3
4/*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
8 *

--- 126 unchanged lines hidden (view full) ---

135 arch_spin_lock(lock);
136}
137
138static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
139{
140 __ticket_spin_unlock_wait(lock);
141}
142
143#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
144#define __raw_write_can_lock(rw) (*(volatile int *)(rw) == 0)
143#define arch_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
144#define arch_write_can_lock(rw) (*(volatile int *)(rw) == 0)
145
146#ifdef ASM_SUPPORTED
147
148static __always_inline void
145
146#ifdef ASM_SUPPORTED
147
148static __always_inline void
149__raw_read_lock_flags(arch_rwlock_t *lock, unsigned long flags)
149arch_read_lock_flags(arch_rwlock_t *lock, unsigned long flags)
150{
151 __asm__ __volatile__ (
152 "tbit.nz p6, p0 = %1,%2\n"
153 "br.few 3f\n"
154 "1:\n"
155 "fetchadd4.rel r2 = [%0], -1;;\n"
156 "(p6) ssm psr.i\n"
157 "2:\n"

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164 "3:\n"
165 "fetchadd4.acq r2 = [%0], 1;;\n"
166 "cmp4.lt p7,p0 = r2, r0\n"
167 "(p7) br.cond.spnt.few 1b\n"
168 : : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
169 : "p6", "p7", "r2", "memory");
170}
171
150{
151 __asm__ __volatile__ (
152 "tbit.nz p6, p0 = %1,%2\n"
153 "br.few 3f\n"
154 "1:\n"
155 "fetchadd4.rel r2 = [%0], -1;;\n"
156 "(p6) ssm psr.i\n"
157 "2:\n"

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164 "3:\n"
165 "fetchadd4.acq r2 = [%0], 1;;\n"
166 "cmp4.lt p7,p0 = r2, r0\n"
167 "(p7) br.cond.spnt.few 1b\n"
168 : : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
169 : "p6", "p7", "r2", "memory");
170}
171
172#define __raw_read_lock(lock) __raw_read_lock_flags(lock, 0)
172#define arch_read_lock(lock) arch_read_lock_flags(lock, 0)
173
174#else /* !ASM_SUPPORTED */
175
173
174#else /* !ASM_SUPPORTED */
175
176#define __raw_read_lock_flags(rw, flags) __raw_read_lock(rw)
176#define arch_read_lock_flags(rw, flags) arch_read_lock(rw)
177
177
178#define __raw_read_lock(rw) \
178#define arch_read_lock(rw) \
179do { \
180 arch_rwlock_t *__read_lock_ptr = (rw); \
181 \
182 while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
183 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
184 while (*(volatile int *)__read_lock_ptr < 0) \
185 cpu_relax(); \
186 } \
187} while (0)
188
189#endif /* !ASM_SUPPORTED */
190
179do { \
180 arch_rwlock_t *__read_lock_ptr = (rw); \
181 \
182 while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
183 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
184 while (*(volatile int *)__read_lock_ptr < 0) \
185 cpu_relax(); \
186 } \
187} while (0)
188
189#endif /* !ASM_SUPPORTED */
190
191#define __raw_read_unlock(rw) \
191#define arch_read_unlock(rw) \
192do { \
193 arch_rwlock_t *__read_lock_ptr = (rw); \
194 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
195} while (0)
196
197#ifdef ASM_SUPPORTED
198
199static __always_inline void
192do { \
193 arch_rwlock_t *__read_lock_ptr = (rw); \
194 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
195} while (0)
196
197#ifdef ASM_SUPPORTED
198
199static __always_inline void
200__raw_write_lock_flags(arch_rwlock_t *lock, unsigned long flags)
200arch_write_lock_flags(arch_rwlock_t *lock, unsigned long flags)
201{
202 __asm__ __volatile__ (
203 "tbit.nz p6, p0 = %1, %2\n"
204 "mov ar.ccv = r0\n"
205 "dep r29 = -1, r0, 31, 1\n"
206 "br.few 3f;;\n"
207 "1:\n"
208 "(p6) ssm psr.i\n"

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216 "3:\n"
217 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"
218 "cmp4.eq p0,p7 = r0, r2\n"
219 "(p7) br.cond.spnt.few 1b;;\n"
220 : : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
221 : "ar.ccv", "p6", "p7", "r2", "r29", "memory");
222}
223
201{
202 __asm__ __volatile__ (
203 "tbit.nz p6, p0 = %1, %2\n"
204 "mov ar.ccv = r0\n"
205 "dep r29 = -1, r0, 31, 1\n"
206 "br.few 3f;;\n"
207 "1:\n"
208 "(p6) ssm psr.i\n"

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216 "3:\n"
217 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"
218 "cmp4.eq p0,p7 = r0, r2\n"
219 "(p7) br.cond.spnt.few 1b;;\n"
220 : : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
221 : "ar.ccv", "p6", "p7", "r2", "r29", "memory");
222}
223
224#define __raw_write_lock(rw) __raw_write_lock_flags(rw, 0)
224#define arch_write_lock(rw) arch_write_lock_flags(rw, 0)
225
225
226#define __raw_write_trylock(rw) \
226#define arch_write_trylock(rw) \
227({ \
228 register long result; \
229 \
230 __asm__ __volatile__ ( \
231 "mov ar.ccv = r0\n" \
232 "dep r29 = -1, r0, 31, 1;;\n" \
233 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
234 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
235 (result == 0); \
236})
237
227({ \
228 register long result; \
229 \
230 __asm__ __volatile__ ( \
231 "mov ar.ccv = r0\n" \
232 "dep r29 = -1, r0, 31, 1;;\n" \
233 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
234 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
235 (result == 0); \
236})
237
238static inline void __raw_write_unlock(arch_rwlock_t *x)
238static inline void arch_write_unlock(arch_rwlock_t *x)
239{
240 u8 *y = (u8 *)x;
241 barrier();
242 asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
243}
244
245#else /* !ASM_SUPPORTED */
246
239{
240 u8 *y = (u8 *)x;
241 barrier();
242 asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
243}
244
245#else /* !ASM_SUPPORTED */
246
247#define __raw_write_lock_flags(l, flags) __raw_write_lock(l)
247#define arch_write_lock_flags(l, flags) arch_write_lock(l)
248
248
249#define __raw_write_lock(l) \
249#define arch_write_lock(l) \
250({ \
251 __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
252 __u32 *ia64_write_lock_ptr = (__u32 *) (l); \
253 do { \
254 while (*ia64_write_lock_ptr) \
255 ia64_barrier(); \
256 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
257 } while (ia64_val); \
258})
259
250({ \
251 __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
252 __u32 *ia64_write_lock_ptr = (__u32 *) (l); \
253 do { \
254 while (*ia64_write_lock_ptr) \
255 ia64_barrier(); \
256 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
257 } while (ia64_val); \
258})
259
260#define __raw_write_trylock(rw) \
260#define arch_write_trylock(rw) \
261({ \
262 __u64 ia64_val; \
263 __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
264 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
265 (ia64_val == 0); \
266})
267
261({ \
262 __u64 ia64_val; \
263 __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
264 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
265 (ia64_val == 0); \
266})
267
268static inline void __raw_write_unlock(arch_rwlock_t *x)
268static inline void arch_write_unlock(arch_rwlock_t *x)
269{
270 barrier();
271 x->write_lock = 0;
272}
273
274#endif /* !ASM_SUPPORTED */
275
269{
270 barrier();
271 x->write_lock = 0;
272}
273
274#endif /* !ASM_SUPPORTED */
275
276static inline int __raw_read_trylock(arch_rwlock_t *x)
276static inline int arch_read_trylock(arch_rwlock_t *x)
277{
278 union {
279 arch_rwlock_t lock;
280 __u32 word;
281 } old, new;
282 old.lock = new.lock = *x;
283 old.lock.write_lock = new.lock.write_lock = 0;
284 ++new.lock.read_counter;
285 return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
286}
287
288#define arch_spin_relax(lock) cpu_relax()
289#define arch_read_relax(lock) cpu_relax()
290#define arch_write_relax(lock) cpu_relax()
291
292#endif /* _ASM_IA64_SPINLOCK_H */
277{
278 union {
279 arch_rwlock_t lock;
280 __u32 word;
281 } old, new;
282 old.lock = new.lock = *x;
283 old.lock.write_lock = new.lock.write_lock = 0;
284 ++new.lock.read_counter;
285 return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
286}
287
288#define arch_spin_relax(lock) cpu_relax()
289#define arch_read_relax(lock) cpu_relax()
290#define arch_write_relax(lock) cpu_relax()
291
292#endif /* _ASM_IA64_SPINLOCK_H */