| entry.h (bf241682936293291dcf40fd93cdd0f5e6222902) | entry.h (f62e31623d718a7c20d9da98de48361624d7360a) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4#ifndef __ASM_CSKY_ENTRY_H 5#define __ASM_CSKY_ENTRY_H 6 7#include <asm/setup.h> 8#include <abi/regdef.h> --- 130 unchanged lines hidden (view full) --- 139 cpwcr \rx, cpcr4 140.endm 141 142.macro WR_MCIR rx 143 cpwcr \rx, cpcr8 144.endm 145 146.macro SETUP_MMU rx | 1/* SPDX-License-Identifier: GPL-2.0 */ 2// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4#ifndef __ASM_CSKY_ENTRY_H 5#define __ASM_CSKY_ENTRY_H 6 7#include <asm/setup.h> 8#include <abi/regdef.h> --- 130 unchanged lines hidden (view full) --- 139 cpwcr \rx, cpcr4 140.endm 141 142.macro WR_MCIR rx 143 cpwcr \rx, cpcr8 144.endm 145 146.macro SETUP_MMU rx |
| 147 lrw \rx, PHYS_OFFSET | 0xe | 147 /* Select MMU as co-processor */ 148 cpseti cp15 149 150 /* 151 * cpcr30 format: 152 * 31 - 29 | 28 - 4 | 3 | 2 | 1 | 0 153 * BA Reserved C D V 154 */ 155 cprcr \rx, cpcr30 156 lsri \rx, 28 157 lsli \rx, 28 158 addi \rx, 0xe |
| 148 cpwcr \rx, cpcr30 | 159 cpwcr \rx, cpcr30 |
| 149 lrw \rx, (PHYS_OFFSET + 0x20000000) | 0xe | 160 161 lsri \rx, 28 162 addi \rx, 2 163 lsli \rx, 28 164 addi \rx, 0xe |
| 150 cpwcr \rx, cpcr31 151.endm 152 153.macro ANDI_R3 rx, imm 154 lsri \rx, 3 155 andi \rx, (\imm >> 3) 156.endm 157#endif /* __ASM_CSKY_ENTRY_H */ | 165 cpwcr \rx, cpcr31 166.endm 167 168.macro ANDI_R3 rx, imm 169 lsri \rx, 3 170 andi \rx, (\imm >> 3) 171.endm 172#endif /* __ASM_CSKY_ENTRY_H */ |