| head.S (734d1ece37fbf3d2ddfc71bc6c69e0fe35f02542) | head.S (2475ff9d2c6ea3bbfed55c4635426c371f9ad327) |
|---|---|
| 1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> --- 68 unchanged lines hidden (view full) --- 77#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF 78#else 79#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED 80#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S 81#endif 82 83#ifdef CONFIG_ARM64_64K_PAGES 84#define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS | 1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> --- 68 unchanged lines hidden (view full) --- 77#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF 78#else 79#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED 80#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S 81#endif 82 83#ifdef CONFIG_ARM64_64K_PAGES 84#define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS |
| 85#define IO_MMUFLAGS PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_XN | PTE_FLAGS | |
| 86#else 87#define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS | 85#else 86#define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS |
| 88#define IO_MMUFLAGS PMD_ATTRINDX(MT_DEVICE_nGnRE) | PMD_SECT_XN | PMD_FLAGS | |
| 89#endif 90 91/* 92 * Kernel startup entry point. 93 * --------------------------- 94 * 95 * The requirements are: 96 * MMU = off, D-cache = off, I-cache = on or off, --- 266 unchanged lines hidden (view full) --- 363 .endm 364 365/* 366 * Setup the initial page tables. We only setup the barest amount which is 367 * required to get the kernel running. The following sections are required: 368 * - identity mapping to enable the MMU (low address, TTBR0) 369 * - first few MB of the kernel linear mapping to jump to once the MMU has 370 * been enabled, including the FDT blob (TTBR1) | 87#endif 88 89/* 90 * Kernel startup entry point. 91 * --------------------------- 92 * 93 * The requirements are: 94 * MMU = off, D-cache = off, I-cache = on or off, --- 266 unchanged lines hidden (view full) --- 361 .endm 362 363/* 364 * Setup the initial page tables. We only setup the barest amount which is 365 * required to get the kernel running. The following sections are required: 366 * - identity mapping to enable the MMU (low address, TTBR0) 367 * - first few MB of the kernel linear mapping to jump to once the MMU has 368 * been enabled, including the FDT blob (TTBR1) |
| 369 * - UART mapping if CONFIG_EARLY_PRINTK is enabled (TTBR1) |
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| 371 */ 372__create_page_tables: 373 pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses 374 375 /* 376 * Clear the idmap and swapper page tables. 377 */ 378 mov x0, x25 --- 36 unchanged lines hidden (view full) --- 415 tst x5, #~((1 << 29) - 1) // within 512MB? 416 csel x21, xzr, x21, ne // zero the FDT pointer 417 b.ne 1f 418 add x5, x5, x6 // __va(FDT blob) 419 add x6, x5, #1 << 21 // 2MB for the FDT blob 420 sub x6, x6, #1 // inclusive range 421 create_block_map x0, x7, x3, x5, x6 4221: | 370 */ 371__create_page_tables: 372 pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses 373 374 /* 375 * Clear the idmap and swapper page tables. 376 */ 377 mov x0, x25 --- 36 unchanged lines hidden (view full) --- 414 tst x5, #~((1 << 29) - 1) // within 512MB? 415 csel x21, xzr, x21, ne // zero the FDT pointer 416 b.ne 1f 417 add x5, x5, x6 // __va(FDT blob) 418 add x6, x5, #1 << 21 // 2MB for the FDT blob 419 sub x6, x6, #1 // inclusive range 420 create_block_map x0, x7, x3, x5, x6 4211: |
| 422#ifdef CONFIG_EARLY_PRINTK 423 /* 424 * Create the pgd entry for the UART mapping. The full mapping is done 425 * later based earlyprintk kernel parameter. 426 */ 427 ldr x5, =EARLYCON_IOBASE // UART virtual address 428 add x0, x26, #2 * PAGE_SIZE // section table address 429 create_pgd_entry x26, x0, x5, x6, x7 430#endif |
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| 423 ret 424ENDPROC(__create_page_tables) 425 .ltorg 426 427 .align 3 428 .type __switch_data, %object 429__switch_data: 430 .quad __mmap_switched --- 107 unchanged lines hidden --- | 431 ret 432ENDPROC(__create_page_tables) 433 .ltorg 434 435 .align 3 436 .type __switch_data, %object 437__switch_data: 438 .quad __mmap_switched --- 107 unchanged lines hidden --- |