traps.h (cdd38c5f1ce4398ec58fec95904b75824daab7b5) | traps.h (8d56e5c5a99ce1d17d39ce5a8260e42c2a2d7682) |
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1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Based on arch/arm/include/asm/traps.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 */ 7#ifndef __ASM_TRAP_H 8#define __ASM_TRAP_H --- 10 unchanged lines hidden (view full) --- 19 u32 instr_val; 20 u64 pstate_mask; 21 u64 pstate_val; 22 int (*fn)(struct pt_regs *regs, u32 instr); 23}; 24 25void register_undef_hook(struct undef_hook *hook); 26void unregister_undef_hook(struct undef_hook *hook); | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Based on arch/arm/include/asm/traps.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 */ 7#ifndef __ASM_TRAP_H 8#define __ASM_TRAP_H --- 10 unchanged lines hidden (view full) --- 19 u32 instr_val; 20 u64 pstate_mask; 21 u64 pstate_val; 22 int (*fn)(struct pt_regs *regs, u32 instr); 23}; 24 25void register_undef_hook(struct undef_hook *hook); 26void unregister_undef_hook(struct undef_hook *hook); |
27void force_signal_inject(int signal, int code, unsigned long address, unsigned int err); | 27void force_signal_inject(int signal, int code, unsigned long address, unsigned long err); |
28void arm64_notify_segfault(unsigned long addr); 29void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str); 30void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str); 31void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str); 32 33/* 34 * Move regs->pc to next instruction and do necessary setup before it 35 * is executed. --- 16 unchanged lines hidden (view full) --- 52 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit 53 * to indicate whether this ESR has a RAS encoding. CPUs without this feature 54 * have a ISS-Valid bit in the same position. 55 * If this bit is set, we know its not a RAS SError. 56 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS 57 * errors share the same encoding as an all-zeros encoding from a CPU that 58 * doesn't support RAS. 59 */ | 28void arm64_notify_segfault(unsigned long addr); 29void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str); 30void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str); 31void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str); 32 33/* 34 * Move regs->pc to next instruction and do necessary setup before it 35 * is executed. --- 16 unchanged lines hidden (view full) --- 52 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit 53 * to indicate whether this ESR has a RAS encoding. CPUs without this feature 54 * have a ISS-Valid bit in the same position. 55 * If this bit is set, we know its not a RAS SError. 56 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS 57 * errors share the same encoding as an all-zeros encoding from a CPU that 58 * doesn't support RAS. 59 */ |
60static inline bool arm64_is_ras_serror(u32 esr) | 60static inline bool arm64_is_ras_serror(unsigned long esr) |
61{ 62 WARN_ON(preemptible()); 63 64 if (esr & ESR_ELx_IDS) 65 return false; 66 67 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) 68 return true; 69 else 70 return false; 71} 72 73/* 74 * Return the AET bits from a RAS SError's ESR. 75 * 76 * It is implementation defined whether Uncategorized errors are containable. 77 * We treat them as Uncontainable. 78 * Non-RAS SError's are reported as Uncontained/Uncategorized. 79 */ | 61{ 62 WARN_ON(preemptible()); 63 64 if (esr & ESR_ELx_IDS) 65 return false; 66 67 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) 68 return true; 69 else 70 return false; 71} 72 73/* 74 * Return the AET bits from a RAS SError's ESR. 75 * 76 * It is implementation defined whether Uncategorized errors are containable. 77 * We treat them as Uncontainable. 78 * Non-RAS SError's are reported as Uncontained/Uncategorized. 79 */ |
80static inline u32 arm64_ras_serror_get_severity(u32 esr) | 80static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr) |
81{ | 81{ |
82 u32 aet = esr & ESR_ELx_AET; | 82 unsigned long aet = esr & ESR_ELx_AET; |
83 84 if (!arm64_is_ras_serror(esr)) { 85 /* Not a RAS error, we can't interpret the ESR. */ 86 return ESR_ELx_AET_UC; 87 } 88 89 /* 90 * AET is RES0 if 'the value returned in the DFSC field is not 91 * [ESR_ELx_FSC_SERROR]' 92 */ 93 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) { 94 /* No severity information : Uncategorized */ 95 return ESR_ELx_AET_UC; 96 } 97 98 return aet; 99} 100 | 83 84 if (!arm64_is_ras_serror(esr)) { 85 /* Not a RAS error, we can't interpret the ESR. */ 86 return ESR_ELx_AET_UC; 87 } 88 89 /* 90 * AET is RES0 if 'the value returned in the DFSC field is not 91 * [ESR_ELx_FSC_SERROR]' 92 */ 93 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) { 94 /* No severity information : Uncategorized */ 95 return ESR_ELx_AET_UC; 96 } 97 98 return aet; 99} 100 |
101bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr); 102void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr); | 101bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr); 102void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr); |
103#endif | 103#endif |