| sysreg.h (d95c3885865b71e56d8d60c8617f2ce1f0fa079d) | sysreg.h (fdec2a9ef853172529baaa192673b4cdb9a44fac) |
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| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 --- 177 unchanged lines hidden (view full) --- 186#define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 187#define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 188#define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 189#define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 190 191#define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 192#define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 193 | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 --- 177 unchanged lines hidden (view full) --- 186#define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 187#define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 188#define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 189#define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 190 191#define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 192#define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 193 |
| 194#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 195#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 196 |
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| 194#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 195 196#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 197#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 198#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 199 200#define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 201#define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) --- 175 unchanged lines hidden (view full) --- 377#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 378 379#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 380 381#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 382#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 383#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 384 | 197#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 198 199#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 200#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 201#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 202 203#define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 204#define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) --- 175 unchanged lines hidden (view full) --- 380#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 381 382#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 383 384#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 385#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 386#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 387 |
| 388#define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 389#define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 390 |
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| 385#define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 386#define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 387#define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 388 389#define __PMEV_op2(n) ((n) & 0x7) 390#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 391#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 392#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 393#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 394 | 391#define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 392#define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 393#define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 394 395#define __PMEV_op2(n) ((n) & 0x7) 396#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 397#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 398#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 399#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 400 |
| 395#define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) | 401#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) |
| 396 397#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) | 402 403#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) |
| 398 | |
| 399#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) | 404#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) |
| 405#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 406#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) |
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| 400#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) | 407#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) |
| 408#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) |
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| 401#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 402#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) | 409#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 410#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) |
| 411#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) |
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| 403 404#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 405#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 406#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 407#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 408#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 409#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 410 --- 28 unchanged lines hidden (view full) --- 439#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 440#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 441#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 442#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 443#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 444#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 445 446/* VHE encodings for architectural EL0/1 system registers */ | 412 413#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 414#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 415#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 416#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 417#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 418#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 419 --- 28 unchanged lines hidden (view full) --- 448#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 449#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 450#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 451#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 452#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 453#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 454 455/* VHE encodings for architectural EL0/1 system registers */ |
| 456#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 457#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) |
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| 447#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) | 458#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) |
| 459#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 460#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 461#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 462#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 463#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 464#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 465#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 466#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 467#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 468#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 469#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 470#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 471#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 472#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 473#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 474#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 475#define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 476#define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 477#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 478#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) |
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| 448 449/* Common SCTLR_ELx flags. */ 450#define SCTLR_ELx_DSSBS (_BITUL(44)) 451#define SCTLR_ELx_ENIA (_BITUL(31)) 452#define SCTLR_ELx_ENIB (_BITUL(30)) 453#define SCTLR_ELx_ENDA (_BITUL(27)) 454#define SCTLR_ELx_EE (_BITUL(25)) 455#define SCTLR_ELx_IESB (_BITUL(21)) --- 382 unchanged lines hidden --- | 479 480/* Common SCTLR_ELx flags. */ 481#define SCTLR_ELx_DSSBS (_BITUL(44)) 482#define SCTLR_ELx_ENIA (_BITUL(31)) 483#define SCTLR_ELx_ENIB (_BITUL(30)) 484#define SCTLR_ELx_ENDA (_BITUL(27)) 485#define SCTLR_ELx_EE (_BITUL(25)) 486#define SCTLR_ELx_IESB (_BITUL(21)) --- 382 unchanged lines hidden --- |