| esr.h (82ffd0454bd9bd57780966d47bfd56d579dd4fb3) | esr.h (453b7740ebfda2d84be7fb583c54f0c91c592869) |
|---|---|
| 1/* 2 * Copyright (C) 2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * --- 142 unchanged lines hidden (view full) --- 151#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 152 153/* ESR value templates for specific events */ 154#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI) 155#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 156 ESR_ELx_WFx_ISS_WFI) 157 158/* BRK instruction trap from AArch64 state */ | 1/* 2 * Copyright (C) 2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * --- 142 unchanged lines hidden (view full) --- 151#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 152 153/* ESR value templates for specific events */ 154#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI) 155#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 156 ESR_ELx_WFx_ISS_WFI) 157 158/* BRK instruction trap from AArch64 state */ |
| 159#define ESR_ELx_VAL_BRK64(imm) \ 160 ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \ 161 ((imm) & 0xffff)) | 159#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff |
| 162 163/* ISS field definitions for System instruction traps */ 164#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 165#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 166#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 167#define ESR_ELx_SYS64_ISS_DIR_READ 0x1 168#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 169 --- 174 unchanged lines hidden --- | 160 161/* ISS field definitions for System instruction traps */ 162#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 163#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 164#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 165#define ESR_ELx_SYS64_ISS_DIR_READ 0x1 166#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 167 --- 174 unchanged lines hidden --- |