cache.h (e5451c8f8330e03ad3cfa16048b4daf961af434f) cache.h (02f7760e6e5c3d726cd9622749cdae17c571b9a3)
1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_CACHE_H
17#define __ASM_CACHE_H
18
1/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_CACHE_H
17#define __ASM_CACHE_H
18
19#include <asm/cachetype.h>
19#include <asm/cputype.h>
20
20
21#define CTR_L1IP_SHIFT 14
22#define CTR_L1IP_MASK 3
23#define CTR_CWG_SHIFT 24
24#define CTR_CWG_MASK 15
25
26#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
27
28#define ICACHE_POLICY_VIPT 2
29#define ICACHE_POLICY_PIPT 3
30
21#define L1_CACHE_SHIFT 7
22#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
23
24/*
25 * Memory returned by kmalloc() may be used for DMA, so we must make
26 * sure that all such allocations are cache aligned. Otherwise,
27 * unrelated code may cause parts of the buffer to be read into the
28 * cache before the transfer is done, causing old data to be seen by
29 * the CPU.
30 */
31#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
32
33#ifndef __ASSEMBLY__
34
31#define L1_CACHE_SHIFT 7
32#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
33
34/*
35 * Memory returned by kmalloc() may be used for DMA, so we must make
36 * sure that all such allocations are cache aligned. Otherwise,
37 * unrelated code may cause parts of the buffer to be read into the
38 * cache before the transfer is done, causing old data to be seen by
39 * the CPU.
40 */
41#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
42
43#ifndef __ASSEMBLY__
44
45#include <linux/bitops.h>
46
47#define ICACHEF_ALIASING 0
48extern unsigned long __icache_flags;
49
50/*
51 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
52 * permitted in the I-cache.
53 */
54static inline int icache_is_aliasing(void)
55{
56 return test_bit(ICACHEF_ALIASING, &__icache_flags);
57}
58
59static inline u32 cache_type_cwg(void)
60{
61 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
62}
63
35#define __read_mostly __attribute__((__section__(".data..read_mostly")))
36
37static inline int cache_line_size(void)
38{
39 u32 cwg = cache_type_cwg();
40 return cwg ? 4 << cwg : L1_CACHE_BYTES;
41}
42
43#endif /* __ASSEMBLY__ */
44
45#endif
64#define __read_mostly __attribute__((__section__(".data..read_mostly")))
65
66static inline int cache_line_size(void)
67{
68 u32 cwg = cache_type_cwg();
69 return cwg ? 4 << cwg : L1_CACHE_BYTES;
70}
71
72#endif /* __ASSEMBLY__ */
73
74#endif