zynqmp.dtsi (3effc177f12d5062bf39496aa6db23d29924678b) zynqmp.dtsi (5be4fbbfbec320dfb08530f0297fa2fe7aa1e836)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP
4 *
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 *

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113
114 rproc_1_fw_image: memory@3ef00000 {
115 no-map;
116 reg = <0x0 0x3ef00000 0x0 0x40000>;
117 };
118 };
119
120 zynqmp_ipi: zynqmp_ipi {
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP
4 *
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 *

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113
114 rproc_1_fw_image: memory@3ef00000 {
115 no-map;
116 reg = <0x0 0x3ef00000 0x0 0x40000>;
117 };
118 };
119
120 zynqmp_ipi: zynqmp_ipi {
121 bootph-all;
121 compatible = "xlnx,zynqmp-ipi-mailbox";
122 interrupt-parent = <&gic>;
123 interrupts = <0 35 4>;
124 xlnx,ipi-id = <0>;
125 #address-cells = <2>;
126 #size-cells = <2>;
127 ranges;
128
129 ipi_mailbox_pmu1: mailbox@ff9905c0 {
122 compatible = "xlnx,zynqmp-ipi-mailbox";
123 interrupt-parent = <&gic>;
124 interrupts = <0 35 4>;
125 xlnx,ipi-id = <0>;
126 #address-cells = <2>;
127 #size-cells = <2>;
128 ranges;
129
130 ipi_mailbox_pmu1: mailbox@ff9905c0 {
131 bootph-all;
130 reg = <0x0 0xff9905c0 0x0 0x20>,
131 <0x0 0xff9905e0 0x0 0x20>,
132 <0x0 0xff990e80 0x0 0x20>,
133 <0x0 0xff990ea0 0x0 0x20>;
134 reg-names = "local_request_region",
135 "local_response_region",
136 "remote_request_region",
137 "remote_response_region";
138 #mbox-cells = <1>;
139 xlnx,ipi-id = <4>;
140 };
141 };
142
143 dcc: dcc {
144 compatible = "arm,dcc";
145 status = "disabled";
132 reg = <0x0 0xff9905c0 0x0 0x20>,
133 <0x0 0xff9905e0 0x0 0x20>,
134 <0x0 0xff990e80 0x0 0x20>,
135 <0x0 0xff990ea0 0x0 0x20>;
136 reg-names = "local_request_region",
137 "local_response_region",
138 "remote_request_region",
139 "remote_response_region";
140 #mbox-cells = <1>;
141 xlnx,ipi-id = <4>;
142 };
143 };
144
145 dcc: dcc {
146 compatible = "arm,dcc";
147 status = "disabled";
148 bootph-all;
146 };
147
148 pmu {
149 compatible = "arm,armv8-pmuv3";
150 interrupt-parent = <&gic>;
151 interrupts = <0 143 4>,
152 <0 144 4>,
153 <0 145 4>,

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159 method = "smc";
160 };
161
162 firmware {
163 zynqmp_firmware: zynqmp-firmware {
164 compatible = "xlnx,zynqmp-firmware";
165 #power-domain-cells = <1>;
166 method = "smc";
149 };
150
151 pmu {
152 compatible = "arm,armv8-pmuv3";
153 interrupt-parent = <&gic>;
154 interrupts = <0 143 4>,
155 <0 144 4>,
156 <0 145 4>,

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162 method = "smc";
163 };
164
165 firmware {
166 zynqmp_firmware: zynqmp-firmware {
167 compatible = "xlnx,zynqmp-firmware";
168 #power-domain-cells = <1>;
169 method = "smc";
170 bootph-all;
167
168 zynqmp_power: zynqmp-power {
171
172 zynqmp_power: zynqmp-power {
173 bootph-all;
169 compatible = "xlnx,zynqmp-power";
170 interrupt-parent = <&gic>;
171 interrupts = <0 35 4>;
172 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
173 mbox-names = "tx", "rx";
174 };
175
176 nvmem_firmware {

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240 compatible = "xlnx,zynqmp-r5f";
241 power-domains = <&zynqmp_firmware PD_RPU_1>;
242 memory-region = <&rproc_1_fw_image>;
243 };
244 };
245
246 amba: axi {
247 compatible = "simple-bus";
174 compatible = "xlnx,zynqmp-power";
175 interrupt-parent = <&gic>;
176 interrupts = <0 35 4>;
177 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
178 mbox-names = "tx", "rx";
179 };
180
181 nvmem_firmware {

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245 compatible = "xlnx,zynqmp-r5f";
246 power-domains = <&zynqmp_firmware PD_RPU_1>;
247 memory-region = <&rproc_1_fw_image>;
248 };
249 };
250
251 amba: axi {
252 compatible = "simple-bus";
253 bootph-all;
248 #address-cells = <2>;
249 #size-cells = <2>;
250 ranges;
251
252 can0: can@ff060000 {
253 compatible = "xlnx,zynq-can-1.0";
254 status = "disabled";
255 clock-names = "can_clk", "pclk";

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679 pcie_intc: legacy-interrupt-controller {
680 interrupt-controller;
681 #address-cells = <0>;
682 #interrupt-cells = <1>;
683 };
684 };
685
686 qspi: spi@ff0f0000 {
254 #address-cells = <2>;
255 #size-cells = <2>;
256 ranges;
257
258 can0: can@ff060000 {
259 compatible = "xlnx,zynq-can-1.0";
260 status = "disabled";
261 clock-names = "can_clk", "pclk";

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685 pcie_intc: legacy-interrupt-controller {
686 interrupt-controller;
687 #address-cells = <0>;
688 #interrupt-cells = <1>;
689 };
690 };
691
692 qspi: spi@ff0f0000 {
693 bootph-all;
687 compatible = "xlnx,zynqmp-qspi-1.0";
688 status = "disabled";
689 clock-names = "ref_clk", "pclk";
690 interrupts = <0 15 4>;
691 interrupt-parent = <&gic>;
692 num-cs = <1>;
693 reg = <0x0 0xff0f0000 0x0 0x1000>,
694 <0x0 0xc0000000 0x0 0x8000000>;

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725 interrupts = <0 133 4>;
726 power-domains = <&zynqmp_firmware PD_SATA>;
727 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
728 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
729 <&smmu 0x4c2>, <&smmu 0x4c3>;
730 };
731
732 sdhci0: mmc@ff160000 {
694 compatible = "xlnx,zynqmp-qspi-1.0";
695 status = "disabled";
696 clock-names = "ref_clk", "pclk";
697 interrupts = <0 15 4>;
698 interrupt-parent = <&gic>;
699 num-cs = <1>;
700 reg = <0x0 0xff0f0000 0x0 0x1000>,
701 <0x0 0xc0000000 0x0 0x8000000>;

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732 interrupts = <0 133 4>;
733 power-domains = <&zynqmp_firmware PD_SATA>;
734 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
735 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
736 <&smmu 0x4c2>, <&smmu 0x4c3>;
737 };
738
739 sdhci0: mmc@ff160000 {
740 bootph-all;
733 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
734 status = "disabled";
735 interrupt-parent = <&gic>;
736 interrupts = <0 48 4>;
737 reg = <0x0 0xff160000 0x0 0x1000>;
738 clock-names = "clk_xin", "clk_ahb";
739 iommus = <&smmu 0x870>;
740 #clock-cells = <1>;
741 clock-output-names = "clk_out_sd0", "clk_in_sd0";
742 power-domains = <&zynqmp_firmware PD_SD_0>;
743 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
744 };
745
746 sdhci1: mmc@ff170000 {
741 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
742 status = "disabled";
743 interrupt-parent = <&gic>;
744 interrupts = <0 48 4>;
745 reg = <0x0 0xff160000 0x0 0x1000>;
746 clock-names = "clk_xin", "clk_ahb";
747 iommus = <&smmu 0x870>;
748 #clock-cells = <1>;
749 clock-output-names = "clk_out_sd0", "clk_in_sd0";
750 power-domains = <&zynqmp_firmware PD_SD_0>;
751 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
752 };
753
754 sdhci1: mmc@ff170000 {
755 bootph-all;
747 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
748 status = "disabled";
749 interrupt-parent = <&gic>;
750 interrupts = <0 49 4>;
751 reg = <0x0 0xff170000 0x0 0x1000>;
752 clock-names = "clk_xin", "clk_ahb";
753 iommus = <&smmu 0x871>;
754 #clock-cells = <1>;

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831 interrupt-parent = <&gic>;
832 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
833 reg = <0x0 0xff140000 0x0 0x1000>;
834 timer-width = <32>;
835 power-domains = <&zynqmp_firmware PD_TTC_3>;
836 };
837
838 uart0: serial@ff000000 {
756 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
757 status = "disabled";
758 interrupt-parent = <&gic>;
759 interrupts = <0 49 4>;
760 reg = <0x0 0xff170000 0x0 0x1000>;
761 clock-names = "clk_xin", "clk_ahb";
762 iommus = <&smmu 0x871>;
763 #clock-cells = <1>;

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840 interrupt-parent = <&gic>;
841 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
842 reg = <0x0 0xff140000 0x0 0x1000>;
843 timer-width = <32>;
844 power-domains = <&zynqmp_firmware PD_TTC_3>;
845 };
846
847 uart0: serial@ff000000 {
848 bootph-all;
839 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
840 status = "disabled";
841 interrupt-parent = <&gic>;
842 interrupts = <0 21 4>;
843 reg = <0x0 0xff000000 0x0 0x1000>;
844 clock-names = "uart_clk", "pclk";
845 power-domains = <&zynqmp_firmware PD_UART_0>;
846 };
847
848 uart1: serial@ff010000 {
849 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
850 status = "disabled";
851 interrupt-parent = <&gic>;
852 interrupts = <0 21 4>;
853 reg = <0x0 0xff000000 0x0 0x1000>;
854 clock-names = "uart_clk", "pclk";
855 power-domains = <&zynqmp_firmware PD_UART_0>;
856 };
857
858 uart1: serial@ff010000 {
859 bootph-all;
849 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
850 status = "disabled";
851 interrupt-parent = <&gic>;
852 interrupts = <0 22 4>;
853 reg = <0x0 0xff010000 0x0 0x1000>;
854 clock-names = "uart_clk", "pclk";
855 power-domains = <&zynqmp_firmware PD_UART_1>;
856 };

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962 interrupts = <0 122 4>;
963 interrupt-parent = <&gic>;
964 clock-names = "axi_clk";
965 power-domains = <&zynqmp_firmware PD_DP>;
966 #dma-cells = <1>;
967 };
968
969 zynqmp_dpsub: display@fd4a0000 {
860 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
861 status = "disabled";
862 interrupt-parent = <&gic>;
863 interrupts = <0 22 4>;
864 reg = <0x0 0xff010000 0x0 0x1000>;
865 clock-names = "uart_clk", "pclk";
866 power-domains = <&zynqmp_firmware PD_UART_1>;
867 };

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973 interrupts = <0 122 4>;
974 interrupt-parent = <&gic>;
975 clock-names = "axi_clk";
976 power-domains = <&zynqmp_firmware PD_DP>;
977 #dma-cells = <1>;
978 };
979
980 zynqmp_dpsub: display@fd4a0000 {
981 bootph-all;
970 compatible = "xlnx,zynqmp-dpsub-1.7";
971 status = "disabled";
972 reg = <0x0 0xfd4a0000 0x0 0x1000>,
973 <0x0 0xfd4aa000 0x0 0x1000>,
974 <0x0 0xfd4ab000 0x0 0x1000>,
975 <0x0 0xfd4ac000 0x0 0x1000>;
976 reg-names = "dp", "blend", "av_buf", "aud";
977 interrupts = <0 119 4>;

--- 37 unchanged lines hidden --- 		982 compatible = "xlnx,zynqmp-dpsub-1.7";
983 status = "disabled";
984 reg = <0x0 0xfd4a0000 0x0 0x1000>,
985 <0x0 0xfd4aa000 0x0 0x1000>,
986 <0x0 0xfd4ab000 0x0 0x1000>,
987 <0x0 0xfd4ac000 0x0 0x1000>;
988 reg-names = "dp", "blend", "av_buf", "aud";
989 interrupts = <0 119 4>;

--- 37 unchanged lines hidden ---