ums512.dtsi (23410de5796cd49abb3f9b6d377822e18298e0a0) ums512.dtsi (2b4881839a392bf66312685cf1c65cd3487e6ec8)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Unisoc UMS512 SoC DTS file
4 *
5 * Copyright (C) 2021, Unisoc Inc.
6 */
7
8#include <dt-bindings/clock/sprd,ums512-clk.h>

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151 soc: soc {
152 compatible = "simple-bus";
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges;
156
157 gic: interrupt-controller@12000000 {
158 compatible = "arm,gic-v3";
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Unisoc UMS512 SoC DTS file
4 *
5 * Copyright (C) 2021, Unisoc Inc.
6 */
7
8#include <dt-bindings/clock/sprd,ums512-clk.h>

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151 soc: soc {
152 compatible = "simple-bus";
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges;
156
157 gic: interrupt-controller@12000000 {
158 compatible = "arm,gic-v3";
159 reg = <0x0 0x12000000 0 0x20000>, /* GICD */
160 <0x0 0x12040000 0 0x100000>; /* GICR */
159 #interrupt-cells = <3>;
160 #address-cells = <2>;
161 #size-cells = <2>;
162 ranges;
163 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
164 #redistributor-regions = <1>;
165 interrupt-controller;
161 #interrupt-cells = <3>;
162 #address-cells = <2>;
163 #size-cells = <2>;
164 ranges;
165 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
166 #redistributor-regions = <1>;
167 interrupt-controller;
166 reg = <0x0 0x12000000 0 0x20000>, /* GICD */
167 <0x0 0x12040000 0 0x100000>; /* GICR */
168 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
169 };
170
171 ap_ahb_regs: syscon@20100000 {
172 compatible = "sprd,ums512-glbregs", "syscon",
173 "simple-mfd";
174 reg = <0 0x20100000 0 0x4000>;
175 #address-cells = <1>;

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809 etm7_out: endpoint {
810 remote-endpoint =
811 <&funnel_core_in_port7>;
812 };
813 };
814 };
815 };
816
168 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
169 };
170
171 ap_ahb_regs: syscon@20100000 {
172 compatible = "sprd,ums512-glbregs", "syscon",
173 "simple-mfd";
174 reg = <0 0x20100000 0 0x4000>;
175 #address-cells = <1>;

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809 etm7_out: endpoint {
810 remote-endpoint =
811 <&funnel_core_in_port7>;
812 };
813 };
814 };
815 };
816
817
818 apb@70000000 {
819 compatible = "simple-bus";
820 #address-cells = <1>;
821 #size-cells = <1>;
822 ranges = <0 0x0 0x70000000 0x10000000>;
823
824 uart0: serial@0 {
825 compatible = "sprd,ums512-uart",

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833 uart1: serial@100000 {
834 compatible = "sprd,ums512-uart",
835 "sprd,sc9836-uart";
836 reg = <0x100000 0x100>;
837 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&ext_26m>;
839 status = "disabled";
840 };
817 apb@70000000 {
818 compatible = "simple-bus";
819 #address-cells = <1>;
820 #size-cells = <1>;
821 ranges = <0 0x0 0x70000000 0x10000000>;
822
823 uart0: serial@0 {
824 compatible = "sprd,ums512-uart",

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832 uart1: serial@100000 {
833 compatible = "sprd,ums512-uart",
834 "sprd,sc9836-uart";
835 reg = <0x100000 0x100>;
836 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&ext_26m>;
838 status = "disabled";
839 };
841 };
842
840
843 ap-apb {
844 compatible = "simple-bus";
845 #address-cells = <2>;
846 #size-cells = <2>;
847 ranges;
848
849 sdio0: sdio@71100000 {
841 sdio0: mmc@1100000 {
850 compatible = "sprd,sdhci-r11";
842 compatible = "sprd,sdhci-r11";
851 reg = <0 0x71100000 0 0x1000>;
843 reg = <0x1100000 0x1000>;
852 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
853 clock-names = "sdio", "enable";
854 clocks = <&ap_clk CLK_SDIO0_2X>,
855 <&apapb_gate CLK_SDIO0_EB>;
856 assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
857 assigned-clock-parents = <&pll1 CLK_RPLL>;
858 status = "disabled";
859 };
860
844 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
845 clock-names = "sdio", "enable";
846 clocks = <&ap_clk CLK_SDIO0_2X>,
847 <&apapb_gate CLK_SDIO0_EB>;
848 assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
849 assigned-clock-parents = <&pll1 CLK_RPLL>;
850 status = "disabled";
851 };
852
861 sdio3: sdio@71400000 {
853 sdio3: mmc@1400000 {
862 compatible = "sprd,sdhci-r11";
854 compatible = "sprd,sdhci-r11";
863 reg = <0 0x71400000 0 0x1000>;
855 reg = <0x1400000 0x1000>;
864 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
865 clock-names = "sdio", "enable";
866 clocks = <&ap_clk CLK_EMMC_2X>,
867 <&apapb_gate CLK_EMMC_EB>;
868 assigned-clocks = <&ap_clk CLK_EMMC_2X>;
869 assigned-clock-parents = <&pll1 CLK_RPLL>;
870 status = "disabled";
871 };
872 };
873
856 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
857 clock-names = "sdio", "enable";
858 clocks = <&ap_clk CLK_EMMC_2X>,
859 <&apapb_gate CLK_EMMC_EB>;
860 assigned-clocks = <&ap_clk CLK_EMMC_2X>;
861 assigned-clock-parents = <&pll1 CLK_RPLL>;
862 status = "disabled";
863 };
864 };
865
874 aon {
866 aon: bus@32000000 {
875 compatible = "simple-bus";
867 compatible = "simple-bus";
876 #address-cells = <2>;
877 #size-cells = <2>;
878 ranges;
868 #address-cells = <1>;
869 #size-cells = <1>;
870 ranges = <0 0x0 0x32000000 0x1000000>;
879
871
880 adi_bus: spi@32100000 {
872 adi_bus: spi@100000 {
881 compatible = "sprd,ums512-adi";
873 compatible = "sprd,ums512-adi";
882 reg = <0 0x32100000 0 0x100000>;
874 reg = <0x100000 0x100000>;
883 #address-cells = <1>;
884 #size-cells = <0>;
885 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
886 <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
887 <35 0x19b8>, <39 0x19ac>;
888 };
889 };
890 };
891
875 #address-cells = <1>;
876 #size-cells = <0>;
877 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
878 <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
879 <35 0x19b8>, <39 0x19ac>;
880 };
881 };
882 };
883
892 ext_26m: ext-26m {
884 ext_26m: clk-26m {
893 compatible = "fixed-clock";
894 #clock-cells = <0>;
895 clock-frequency = <26000000>;
896 clock-output-names = "ext-26m";
897 };
898
885 compatible = "fixed-clock";
886 #clock-cells = <0>;
887 clock-frequency = <26000000>;
888 clock-output-names = "ext-26m";
889 };
890
899 ext_32k: ext-32k {
891 ext_32k: clk-32k {
900 compatible = "fixed-clock";
901 #clock-cells = <0>;
902 clock-frequency = <32768>;
903 clock-output-names = "ext-32k";
904 };
905
892 compatible = "fixed-clock";
893 #clock-cells = <0>;
894 clock-frequency = <32768>;
895 clock-output-names = "ext-32k";
896 };
897
906 ext_4m: ext-4m {
898 ext_4m: clk-4m {
907 compatible = "fixed-clock";
908 #clock-cells = <0>;
909 clock-frequency = <4000000>;
910 clock-output-names = "ext-4m";
911 };
912
899 compatible = "fixed-clock";
900 #clock-cells = <0>;
901 clock-frequency = <4000000>;
902 clock-output-names = "ext-4m";
903 };
904
913 rco_100m: rco-100m {
905 rco_100m: clk-100m {
914 compatible = "fixed-clock";
915 #clock-cells = <0>;
916 clock-frequency = <100000000>;
917 clock-output-names = "rco-100m";
918 };
919};
906 compatible = "fixed-clock";
907 #clock-cells = <0>;
908 clock-frequency = <100000000>;
909 clock-output-names = "rco-100m";
910 };
911};