r8a77961.dtsi (44b615ac9fab16d1552cd8360454077d411e3c35) r8a77961.dtsi (659b38203f04f5c3d1dc60f1a3e54b582ad3841c)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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47 };
48
49 cluster0_opp: opp_table0 {
50 compatible = "operating-points-v2";
51 opp-shared;
52
53 opp-500000000 {
54 opp-hz = /bits/ 64 <500000000>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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47 };
48
49 cluster0_opp: opp_table0 {
50 compatible = "operating-points-v2";
51 opp-shared;
52
53 opp-500000000 {
54 opp-hz = /bits/ 64 <500000000>;
55 opp-microvolt = <820000>;
55 opp-microvolt = <830000>;
56 clock-latency-ns = <300000>;
57 };
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <300000>;
57 };
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <820000>;
60 opp-microvolt = <830000>;
61 clock-latency-ns = <300000>;
62 };
63 opp-1500000000 {
64 opp-hz = /bits/ 64 <1500000000>;
61 clock-latency-ns = <300000>;
62 };
63 opp-1500000000 {
64 opp-hz = /bits/ 64 <1500000000>;
65 opp-microvolt = <820000>;
65 opp-microvolt = <830000>;
66 clock-latency-ns = <300000>;
67 opp-suspend;
68 };
69 opp-1600000000 {
70 opp-hz = /bits/ 64 <1600000000>;
71 opp-microvolt = <900000>;
72 clock-latency-ns = <300000>;
73 turbo-mode;

--- 2695 unchanged lines hidden --- 		66 clock-latency-ns = <300000>;
67 opp-suspend;
68 };
69 opp-1600000000 {
70 opp-hz = /bits/ 64 <1600000000>;
71 opp-microvolt = <900000>;
72 clock-latency-ns = <300000>;
73 turbo-mode;

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