r8a77961.dtsi (448cc2fb3a7b327823a9afd374808c37b8e6194f) r8a77961.dtsi (7744b393c95ac470a3ac279fa277e50d947f1bea)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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41
42 /* External CAN clock - to be overridden by boards that provide it */
43 can_clk: can {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <0>;
47 };
48
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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41
42 /* External CAN clock - to be overridden by boards that provide it */
43 can_clk: can {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <0>;
47 };
48
49 cluster0_opp: opp_table0 {
49 cluster0_opp: opp-table-0 {
50 compatible = "operating-points-v2";
51 opp-shared;
52
53 opp-500000000 {
54 opp-hz = /bits/ 64 <500000000>;
55 opp-microvolt = <830000>;
56 clock-latency-ns = <300000>;
57 };

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81 opp-1800000000 {
82 opp-hz = /bits/ 64 <1800000000>;
83 opp-microvolt = <960000>;
84 clock-latency-ns = <300000>;
85 turbo-mode;
86 };
87 };
88
50 compatible = "operating-points-v2";
51 opp-shared;
52
53 opp-500000000 {
54 opp-hz = /bits/ 64 <500000000>;
55 opp-microvolt = <830000>;
56 clock-latency-ns = <300000>;
57 };

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81 opp-1800000000 {
82 opp-hz = /bits/ 64 <1800000000>;
83 opp-microvolt = <960000>;
84 clock-latency-ns = <300000>;
85 turbo-mode;
86 };
87 };
88
89 cluster1_opp: opp_table1 {
89 cluster1_opp: opp-table-1 {
90 compatible = "operating-points-v2";
91 opp-shared;
92
93 opp-800000000 {
94 opp-hz = /bits/ 64 <800000000>;
95 opp-microvolt = <820000>;
96 clock-latency-ns = <300000>;
97 };

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2307 status = "disabled";
2308 };
2309
2310 sdhi0: mmc@ee100000 {
2311 compatible = "renesas,sdhi-r8a77961",
2312 "renesas,rcar-gen3-sdhi";
2313 reg = <0 0xee100000 0 0x2000>;
2314 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
90 compatible = "operating-points-v2";
91 opp-shared;
92
93 opp-800000000 {
94 opp-hz = /bits/ 64 <800000000>;
95 opp-microvolt = <820000>;
96 clock-latency-ns = <300000>;
97 };

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2307 status = "disabled";
2308 };
2309
2310 sdhi0: mmc@ee100000 {
2311 compatible = "renesas,sdhi-r8a77961",
2312 "renesas,rcar-gen3-sdhi";
2313 reg = <0 0xee100000 0 0x2000>;
2314 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2315 clocks = <&cpg CPG_MOD 314>;
2315 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77961_CLK_SD0H>;
2316 clock-names = "core", "clkh";
2316 max-frequency = <200000000>;
2317 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2318 resets = <&cpg 314>;
2319 iommus = <&ipmmu_ds1 32>;
2320 status = "disabled";
2321 };
2322
2323 sdhi1: mmc@ee120000 {
2324 compatible = "renesas,sdhi-r8a77961",
2325 "renesas,rcar-gen3-sdhi";
2326 reg = <0 0xee120000 0 0x2000>;
2327 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2317 max-frequency = <200000000>;
2318 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2319 resets = <&cpg 314>;
2320 iommus = <&ipmmu_ds1 32>;
2321 status = "disabled";
2322 };
2323
2324 sdhi1: mmc@ee120000 {
2325 compatible = "renesas,sdhi-r8a77961",
2326 "renesas,rcar-gen3-sdhi";
2327 reg = <0 0xee120000 0 0x2000>;
2328 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2328 clocks = <&cpg CPG_MOD 313>;
2329 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77961_CLK_SD1H>;
2330 clock-names = "core", "clkh";
2329 max-frequency = <200000000>;
2330 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2331 resets = <&cpg 313>;
2332 iommus = <&ipmmu_ds1 33>;
2333 status = "disabled";
2334 };
2335
2336 sdhi2: mmc@ee140000 {
2337 compatible = "renesas,sdhi-r8a77961",
2338 "renesas,rcar-gen3-sdhi";
2339 reg = <0 0xee140000 0 0x2000>;
2340 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2331 max-frequency = <200000000>;
2332 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2333 resets = <&cpg 313>;
2334 iommus = <&ipmmu_ds1 33>;
2335 status = "disabled";
2336 };
2337
2338 sdhi2: mmc@ee140000 {
2339 compatible = "renesas,sdhi-r8a77961",
2340 "renesas,rcar-gen3-sdhi";
2341 reg = <0 0xee140000 0 0x2000>;
2342 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2341 clocks = <&cpg CPG_MOD 312>;
2343 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77961_CLK_SD2H>;
2344 clock-names = "core", "clkh";
2342 max-frequency = <200000000>;
2343 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2344 resets = <&cpg 312>;
2345 iommus = <&ipmmu_ds1 34>;
2346 status = "disabled";
2347 };
2348
2349 sdhi3: mmc@ee160000 {
2350 compatible = "renesas,sdhi-r8a77961",
2351 "renesas,rcar-gen3-sdhi";
2352 reg = <0 0xee160000 0 0x2000>;
2353 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2345 max-frequency = <200000000>;
2346 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2347 resets = <&cpg 312>;
2348 iommus = <&ipmmu_ds1 34>;
2349 status = "disabled";
2350 };
2351
2352 sdhi3: mmc@ee160000 {
2353 compatible = "renesas,sdhi-r8a77961",
2354 "renesas,rcar-gen3-sdhi";
2355 reg = <0 0xee160000 0 0x2000>;
2356 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2354 clocks = <&cpg CPG_MOD 311>;
2357 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77961_CLK_SD3H>;
2358 clock-names = "core", "clkh";
2355 max-frequency = <200000000>;
2356 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2357 resets = <&cpg 311>;
2358 iommus = <&ipmmu_ds1 35>;
2359 status = "disabled";
2360 };
2361
2362 gic: interrupt-controller@f1010000 {

--- 455 unchanged lines hidden --- 		2359 max-frequency = <200000000>;
2360 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2361 resets = <&cpg 311>;
2362 iommus = <&ipmmu_ds1 35>;
2363 status = "disabled";
2364 };
2365
2366 gic: interrupt-controller@f1010000 {

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