r8a77961.dtsi (35bb28ece90dfb7f72b77ba529f25f79323d9581) r8a77961.dtsi (92c406ed0a7f2810c4498e2b6bea81c6b61c03e8)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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1150 rx-internal-delay-ps = <0>;
1151 tx-internal-delay-ps = <0>;
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1154 status = "disabled";
1155 };
1156
1157 can0: can@e6c30000 {
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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1150 rx-internal-delay-ps = <0>;
1151 tx-internal-delay-ps = <0>;
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1154 status = "disabled";
1155 };
1156
1157 can0: can@e6c30000 {
1158 compatible = "renesas,can-r8a77961",
1159 "renesas,rcar-gen3-can";
1158 reg = <0 0xe6c30000 0 0x1000>;
1160 reg = <0 0xe6c30000 0 0x1000>;
1159 /* placeholder */
1161 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&cpg CPG_MOD 916>,
1163 <&cpg CPG_CORE R8A77961_CLK_CANFD>,
1164 <&can_clk>;
1165 clock-names = "clkp1", "clkp2", "can_clk";
1166 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
1167 assigned-clock-rates = <40000000>;
1168 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1169 resets = <&cpg 916>;
1170 status = "disabled";
1160 };
1161
1162 can1: can@e6c38000 {
1171 };
1172
1173 can1: can@e6c38000 {
1174 compatible = "renesas,can-r8a77961",
1175 "renesas,rcar-gen3-can";
1163 reg = <0 0xe6c38000 0 0x1000>;
1176 reg = <0 0xe6c38000 0 0x1000>;
1164 /* placeholder */
1177 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MOD 915>,
1179 <&cpg CPG_CORE R8A77961_CLK_CANFD>,
1180 <&can_clk>;
1181 clock-names = "clkp1", "clkp2", "can_clk";
1182 assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
1183 assigned-clock-rates = <40000000>;
1184 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1185 resets = <&cpg 915>;
1186 status = "disabled";
1165 };
1166
1167 pwm0: pwm@e6e30000 {
1168 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar";
1169 reg = <0 0xe6e30000 0 8>;
1170 #pwm-cells = <2>;
1171 clocks = <&cpg CPG_MOD 523>;
1172 resets = <&cpg 523>;

--- 1270 unchanged lines hidden --- 		1187 };
1188
1189 pwm0: pwm@e6e30000 {
1190 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar";
1191 reg = <0 0xe6e30000 0 8>;
1192 #pwm-cells = <2>;
1193 clocks = <&cpg CPG_MOD 523>;
1194 resets = <&cpg 523>;

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