r8a774e1.dtsi (52e844ee9a6f460e6160736a43ef13317a91ca74) r8a774e1.dtsi (7744b393c95ac470a3ac279fa277e50d947f1bea)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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42
43 /* External CAN clock - to be overridden by boards that provide it */
44 can_clk: can {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <0>;
48 };
49
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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42
43 /* External CAN clock - to be overridden by boards that provide it */
44 can_clk: can {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <0>;
48 };
49
50 cluster0_opp: opp_table0 {
50 cluster0_opp: opp-table-0 {
51 compatible = "operating-points-v2";
52 opp-shared;
53
54 opp-500000000 {
55 opp-hz = /bits/ 64 <500000000>;
56 opp-microvolt = <820000>;
57 clock-latency-ns = <300000>;
58 };

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64 opp-1500000000 {
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <820000>;
67 clock-latency-ns = <300000>;
68 opp-suspend;
69 };
70 };
71
51 compatible = "operating-points-v2";
52 opp-shared;
53
54 opp-500000000 {
55 opp-hz = /bits/ 64 <500000000>;
56 opp-microvolt = <820000>;
57 clock-latency-ns = <300000>;
58 };

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64 opp-1500000000 {
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <820000>;
67 clock-latency-ns = <300000>;
68 opp-suspend;
69 };
70 };
71
72 cluster1_opp: opp_table1 {
72 cluster1_opp: opp-table-1 {
73 compatible = "operating-points-v2";
74 opp-shared;
75
76 opp-800000000 {
77 opp-hz = /bits/ 64 <800000000>;
78 opp-microvolt = <820000>;
79 clock-latency-ns = <300000>;
80 };

--- 2917 unchanged lines hidden --- 		73 compatible = "operating-points-v2";
74 opp-shared;
75
76 opp-800000000 {
77 opp-hz = /bits/ 64 <800000000>;
78 opp-microvolt = <820000>;
79 clock-latency-ns = <300000>;
80 };

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