r8a774a1.dtsi (52e844ee9a6f460e6160736a43ef13317a91ca74) r8a774a1.dtsi (7744b393c95ac470a3ac279fa277e50d947f1bea)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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53
54 /* External CAN clock - to be overridden by boards that provide it */
55 can_clk: can {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
60
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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53
54 /* External CAN clock - to be overridden by boards that provide it */
55 can_clk: can {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
60
61 cluster0_opp: opp_table0 {
61 cluster0_opp: opp-table-0 {
62 compatible = "operating-points-v2";
63 opp-shared;
64
65 opp-500000000 {
66 opp-hz = /bits/ 64 <500000000>;
67 opp-microvolt = <820000>;
68 clock-latency-ns = <300000>;
69 };

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75 opp-1500000000 {
76 opp-hz = /bits/ 64 <1500000000>;
77 opp-microvolt = <820000>;
78 clock-latency-ns = <300000>;
79 opp-suspend;
80 };
81 };
82
62 compatible = "operating-points-v2";
63 opp-shared;
64
65 opp-500000000 {
66 opp-hz = /bits/ 64 <500000000>;
67 opp-microvolt = <820000>;
68 clock-latency-ns = <300000>;
69 };

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75 opp-1500000000 {
76 opp-hz = /bits/ 64 <1500000000>;
77 opp-microvolt = <820000>;
78 clock-latency-ns = <300000>;
79 opp-suspend;
80 };
81 };
82
83 cluster1_opp: opp_table1 {
83 cluster1_opp: opp-table-1 {
84 compatible = "operating-points-v2";
85 opp-shared;
86
87 opp-800000000 {
88 opp-hz = /bits/ 64 <800000000>;
89 opp-microvolt = <820000>;
90 clock-latency-ns = <300000>;
91 };

--- 2784 unchanged lines hidden --- 		84 compatible = "operating-points-v2";
85 opp-shared;
86
87 opp-800000000 {
88 opp-hz = /bits/ 64 <800000000>;
89 opp-microvolt = <820000>;
90 clock-latency-ns = <300000>;
91 };

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