sc8180x.dtsi (c900529f3d9161bfde5cca0754f83b4d3c3e0220) sc8180x.dtsi (8d0c268ffcb3dbec0092e46e3b9ce04003f3d6b4)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
5 */
6
7#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8#include <dt-bindings/clock/qcom,gcc-sc8180x.h>

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1746 power-domains = <&gcc PCIE_0_GDSC>;
1747
1748 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1750 interconnect-names = "pcie-mem", "cpu-pcie";
1751
1752 phys = <&pcie0_lane>;
1753 phy-names = "pciephy";
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
5 */
6
7#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8#include <dt-bindings/clock/qcom,gcc-sc8180x.h>

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1746 power-domains = <&gcc PCIE_0_GDSC>;
1747
1748 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1750 interconnect-names = "pcie-mem", "cpu-pcie";
1751
1752 phys = <&pcie0_lane>;
1753 phy-names = "pciephy";
1754 dma-coherent;
1754
1755 status = "disabled";
1756 };
1757
1758 pcie0_phy: phy-wrapper@1c06000 {
1759 compatible = "qcom,sc8180x-qmp-pcie-phy";
1760 reg = <0 0x1c06000 0 0x1c0>;
1761 #address-cells = <2>;

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1853 power-domains = <&gcc PCIE_3_GDSC>;
1854
1855 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1856 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1857 interconnect-names = "pcie-mem", "cpu-pcie";
1858
1859 phys = <&pcie3_lane>;
1860 phy-names = "pciephy";
1755
1756 status = "disabled";
1757 };
1758
1759 pcie0_phy: phy-wrapper@1c06000 {
1760 compatible = "qcom,sc8180x-qmp-pcie-phy";
1761 reg = <0 0x1c06000 0 0x1c0>;
1762 #address-cells = <2>;

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1854 power-domains = <&gcc PCIE_3_GDSC>;
1855
1856 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1857 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1858 interconnect-names = "pcie-mem", "cpu-pcie";
1859
1860 phys = <&pcie3_lane>;
1861 phy-names = "pciephy";
1862 dma-coherent;
1861
1862 status = "disabled";
1863 };
1864
1865 pcie3_phy: phy-wrapper@1c0c000 {
1866 compatible = "qcom,sc8180x-qmp-pcie-phy";
1867 reg = <0 0x1c0c000 0 0x1c0>;
1868 #address-cells = <2>;

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1960 power-domains = <&gcc PCIE_1_GDSC>;
1961
1962 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
1963 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1964 interconnect-names = "pcie-mem", "cpu-pcie";
1965
1966 phys = <&pcie1_lane>;
1967 phy-names = "pciephy";
1863
1864 status = "disabled";
1865 };
1866
1867 pcie3_phy: phy-wrapper@1c0c000 {
1868 compatible = "qcom,sc8180x-qmp-pcie-phy";
1869 reg = <0 0x1c0c000 0 0x1c0>;
1870 #address-cells = <2>;

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1962 power-domains = <&gcc PCIE_1_GDSC>;
1963
1964 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
1965 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1966 interconnect-names = "pcie-mem", "cpu-pcie";
1967
1968 phys = <&pcie1_lane>;
1969 phy-names = "pciephy";
1970 dma-coherent;
1968
1969 status = "disabled";
1970 };
1971
1972 pcie1_phy: phy-wrapper@1c16000 {
1973 compatible = "qcom,sc8180x-qmp-pcie-phy";
1974 reg = <0 0x1c16000 0 0x1c0>;
1975 #address-cells = <2>;

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2067 power-domains = <&gcc PCIE_2_GDSC>;
2068
2069 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2070 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
2071 interconnect-names = "pcie-mem", "cpu-pcie";
2072
2073 phys = <&pcie2_lane>;
2074 phy-names = "pciephy";
1971
1972 status = "disabled";
1973 };
1974
1975 pcie1_phy: phy-wrapper@1c16000 {
1976 compatible = "qcom,sc8180x-qmp-pcie-phy";
1977 reg = <0 0x1c16000 0 0x1c0>;
1978 #address-cells = <2>;

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2070 power-domains = <&gcc PCIE_2_GDSC>;
2071
2072 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2073 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
2074 interconnect-names = "pcie-mem", "cpu-pcie";
2075
2076 phys = <&pcie2_lane>;
2077 phy-names = "pciephy";
2078 dma-coherent;
2075
2076 status = "disabled";
2077 };
2078
2079 pcie2_phy: phy-wrapper@1c1c000 {
2080 compatible = "qcom,sc8180x-qmp-pcie-phy";
2081 reg = <0 0x1c1c000 0 0x1c0>;
2082 #address-cells = <2>;

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2080 status = "disabled";
2081 };
2082
2083 pcie2_phy: phy-wrapper@1c1c000 {
2084 compatible = "qcom,sc8180x-qmp-pcie-phy";
2085 reg = <0 0x1c1c000 0 0x1c0>;
2086 #address-cells = <2>;

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