sc8180x.dtsi (0791faebfe750292a8a842b64795a390ca4a3b51) sc8180x.dtsi (b0246331c51e65c1d7c853bc617904058540d47f)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
5 */
6
7#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8#include <dt-bindings/clock/qcom,gcc-sc8180x.h>

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59 L2_0: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
65 compatible = "cache";
66 cache-level = <3>;
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
5 */
6
7#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8#include <dt-bindings/clock/qcom,gcc-sc8180x.h>

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59 L2_0: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
65 compatible = "cache";
66 cache-level = <3>;
67 cache-unified;
67 };
68 };
69 };
70
71 CPU1: cpu@100 {
72 device_type = "cpu";
73 compatible = "qcom,kryo485";
74 reg = <0x0 0x100>;

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293 min-residency-us = <4488>;
294 local-timer-stop;
295 };
296 };
297
298 domain-idle-states {
299 CLUSTER_SLEEP_0: cluster-sleep-0 {
300 compatible = "domain-idle-state";
68 };
69 };
70 };
71
72 CPU1: cpu@100 {
73 device_type = "cpu";
74 compatible = "qcom,kryo485";
75 reg = <0x0 0x100>;

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294 min-residency-us = <4488>;
295 local-timer-stop;
296 };
297 };
298
299 domain-idle-states {
300 CLUSTER_SLEEP_0: cluster-sleep-0 {
301 compatible = "domain-idle-state";
301 arm,psci-suspend-param = <0x4100c244>;
302 arm,psci-suspend-param = <0x4100a344>;
302 entry-latency-us = <3263>;
303 exit-latency-us = <6562>;
304 min-residency-us = <9987>;
305 };
306 };
307 };
308
309 cpu0_opp_table: opp-table-cpu0 {

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2247 opp-177000000 {
2248 opp-hz = /bits/ 64 <177000000>;
2249 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2250 };
2251 };
2252 };
2253
2254 gmu: gmu@2c6a000 {
303 entry-latency-us = <3263>;
304 exit-latency-us = <6562>;
305 min-residency-us = <9987>;
306 };
307 };
308 };
309
310 cpu0_opp_table: opp-table-cpu0 {

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2248 opp-177000000 {
2249 opp-hz = /bits/ 64 <177000000>;
2250 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2251 };
2252 };
2253 };
2254
2255 gmu: gmu@2c6a000 {
2255 compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2256 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2256
2257 reg = <0 0x02c6a000 0 0x30000>,
2258 <0 0x0b290000 0 0x10000>,
2259 <0 0x0b490000 0 0x10000>;
2260 reg-names = "gmu",
2261 "gmu_pdc",
2262 "gmu_pdc_seq";
2263

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2459
2460 #clock-cells = <1>;
2461 #address-cells = <2>;
2462 #size-cells = <2>;
2463 ranges;
2464
2465 status = "disabled";
2466
2257
2258 reg = <0 0x02c6a000 0 0x30000>,
2259 <0 0x0b290000 0 0x10000>,
2260 <0 0x0b490000 0 0x10000>;
2261 reg-names = "gmu",
2262 "gmu_pdc",
2263 "gmu_pdc_seq";
2264

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2460
2461 #clock-cells = <1>;
2462 #address-cells = <2>;
2463 #size-cells = <2>;
2464 ranges;
2465
2466 status = "disabled";
2467
2468 ports {
2469 #address-cells = <1>;
2470 #size-cells = <0>;
2471
2472 port@0 {
2473 reg = <0>;
2474
2475 usb_prim_qmpphy_out: endpoint {};
2476 };
2477
2478 port@2 {
2479 reg = <2>;
2480
2481 usb_prim_qmpphy_dp_in: endpoint {};
2482 };
2483 };
2484
2467 usb_prim_ssphy: usb3-phy@88e9200 {
2468 reg = <0 0x088e9200 0 0x200>,
2469 <0 0x088e9400 0 0x200>,
2470 <0 0x088e9c00 0 0x218>,
2471 <0 0x088e9600 0 0x200>,
2472 <0 0x088e9800 0 0x200>,
2473 <0 0x088e9a00 0 0x100>;
2474 #phy-cells = <0>;

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2508
2509 #clock-cells = <1>;
2510 #address-cells = <2>;
2511 #size-cells = <2>;
2512 ranges;
2513
2514 status = "disabled";
2515
2485 usb_prim_ssphy: usb3-phy@88e9200 {
2486 reg = <0 0x088e9200 0 0x200>,
2487 <0 0x088e9400 0 0x200>,
2488 <0 0x088e9c00 0 0x218>,
2489 <0 0x088e9600 0 0x200>,
2490 <0 0x088e9800 0 0x200>,
2491 <0 0x088e9a00 0 0x100>;
2492 #phy-cells = <0>;

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2526
2527 #clock-cells = <1>;
2528 #address-cells = <2>;
2529 #size-cells = <2>;
2530 ranges;
2531
2532 status = "disabled";
2533
2534 ports {
2535 #address-cells = <1>;
2536 #size-cells = <0>;
2537
2538 port@0 {
2539 reg = <0>;
2540
2541 usb_sec_qmpphy_out: endpoint {};
2542 };
2543
2544 port@2 {
2545 reg = <2>;
2546
2547 usb_sec_qmpphy_dp_in: endpoint {};
2548 };
2549 };
2550
2516 usb_sec_ssphy: usb3-phy@88e9200 {
2517 reg = <0 0x088ee200 0 0x200>,
2518 <0 0x088ee400 0 0x200>,
2519 <0 0x088eec00 0 0x218>,
2520 <0 0x088ee600 0 0x200>,
2521 <0 0x088ee800 0 0x200>,
2522 <0 0x088eea00 0 0x100>;
2523 #phy-cells = <0>;

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2599 compatible = "snps,dwc3";
2600 reg = <0 0x0a600000 0 0xcd00>;
2601 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2602 iommus = <&apps_smmu 0x140 0>;
2603 snps,dis_u2_susphy_quirk;
2604 snps,dis_enblslpm_quirk;
2605 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
2606 phy-names = "usb2-phy", "usb3-phy";
2551 usb_sec_ssphy: usb3-phy@88e9200 {
2552 reg = <0 0x088ee200 0 0x200>,
2553 <0 0x088ee400 0 0x200>,
2554 <0 0x088eec00 0 0x218>,
2555 <0 0x088ee600 0 0x200>,
2556 <0 0x088ee800 0 0x200>,
2557 <0 0x088eea00 0 0x100>;
2558 #phy-cells = <0>;

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2634 compatible = "snps,dwc3";
2635 reg = <0 0x0a600000 0 0xcd00>;
2636 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2637 iommus = <&apps_smmu 0x140 0>;
2638 snps,dis_u2_susphy_quirk;
2639 snps,dis_enblslpm_quirk;
2640 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
2641 phy-names = "usb2-phy", "usb3-phy";
2642
2643 port {
2644 usb_prim_role_switch: endpoint {
2645 };
2646 };
2607 };
2608 };
2609
2610 usb_sec: usb@a8f8800 {
2611 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2612 reg = <0 0x0a8f8800 0 0x400>;
2613
2614 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,

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2651 compatible = "snps,dwc3";
2652 reg = <0 0x0a800000 0 0xcd00>;
2653 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2654 iommus = <&apps_smmu 0x160 0>;
2655 snps,dis_u2_susphy_quirk;
2656 snps,dis_enblslpm_quirk;
2657 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
2658 phy-names = "usb2-phy", "usb3-phy";
2647 };
2648 };
2649
2650 usb_sec: usb@a8f8800 {
2651 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2652 reg = <0 0x0a8f8800 0 0x400>;
2653
2654 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,

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2691 compatible = "snps,dwc3";
2692 reg = <0 0x0a800000 0 0xcd00>;
2693 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2694 iommus = <&apps_smmu 0x160 0>;
2695 snps,dis_u2_susphy_quirk;
2696 snps,dis_enblslpm_quirk;
2697 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
2698 phy-names = "usb2-phy", "usb3-phy";
2699
2700 port {
2701 usb_sec_role_switch: endpoint {
2702 };
2703 };
2659 };
2660 };
2661
2662 mdss: mdss@ae00000 {
2663 compatible = "qcom,sc8180x-mdss";
2664 reg = <0 0x0ae00000 0 0x1000>;
2665 reg-names = "mdss";
2666

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2978 reg = <0>;
2979 dp0_in: endpoint {
2980 remote-endpoint = <&dpu_intf0_out>;
2981 };
2982 };
2983
2984 port@1 {
2985 reg = <1>;
2704 };
2705 };
2706
2707 mdss: mdss@ae00000 {
2708 compatible = "qcom,sc8180x-mdss";
2709 reg = <0 0x0ae00000 0 0x1000>;
2710 reg-names = "mdss";
2711

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3023 reg = <0>;
3024 dp0_in: endpoint {
3025 remote-endpoint = <&dpu_intf0_out>;
3026 };
3027 };
3028
3029 port@1 {
3030 reg = <1>;
3031 mdss_dp0_out: endpoint {
3032 };
2986 };
2987 };
2988
2989 dp0_opp_table: opp-table {
2990 compatible = "operating-points-v2";
2991
2992 opp-160000000 {
2993 opp-hz = /bits/ 64 <160000000>;

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3052 reg = <0>;
3053 dp1_in: endpoint {
3054 remote-endpoint = <&dpu_intf4_out>;
3055 };
3056 };
3057
3058 port@1 {
3059 reg = <1>;
3033 };
3034 };
3035
3036 dp0_opp_table: opp-table {
3037 compatible = "operating-points-v2";
3038
3039 opp-160000000 {
3040 opp-hz = /bits/ 64 <160000000>;

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3099 reg = <0>;
3100 dp1_in: endpoint {
3101 remote-endpoint = <&dpu_intf4_out>;
3102 };
3103 };
3104
3105 port@1 {
3106 reg = <1>;
3107 mdss_dp1_out: endpoint {
3108 };
3060 };
3061 };
3062
3063 dp1_opp_table: opp-table {
3064 compatible = "operating-points-v2";
3065
3066 opp-160000000 {
3067 opp-hz = /bits/ 64 <160000000>;

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3424 timer@17c20000 {
3425 compatible = "arm,armv7-timer-mem";
3426 reg = <0x0 0x17c20000 0x0 0x1000>;
3427
3428 #address-cells = <1>;
3429 #size-cells = <1>;
3430 ranges = <0 0 0 0x20000000>;
3431
3109 };
3110 };
3111
3112 dp1_opp_table: opp-table {
3113 compatible = "operating-points-v2";
3114
3115 opp-160000000 {
3116 opp-hz = /bits/ 64 <160000000>;

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3473 timer@17c20000 {
3474 compatible = "arm,armv7-timer-mem";
3475 reg = <0x0 0x17c20000 0x0 0x1000>;
3476
3477 #address-cells = <1>;
3478 #size-cells = <1>;
3479 ranges = <0 0 0 0x20000000>;
3480
3432 frame@17c21000{
3481 frame@17c21000 {
3433 reg = <0x17c21000 0x1000>,
3434 <0x17c22000 0x1000>;
3435 frame-number = <0>;
3436 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3437 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3438 };
3439
3440 frame@17c23000 {

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3851 cluster-crit {
3852 temperature = <110000>;
3853 hysteresis = <2000>;
3854 type = "critical";
3855 };
3856 };
3857 };
3858
3482 reg = <0x17c21000 0x1000>,
3483 <0x17c22000 0x1000>;
3484 frame-number = <0>;
3485 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3487 };
3488
3489 frame@17c23000 {

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3900 cluster-crit {
3901 temperature = <110000>;
3902 hysteresis = <2000>;
3903 type = "critical";
3904 };
3905 };
3906 };
3907
3859 gpu-thermal-top {
3908 gpu-top-thermal {
3860 polling-delay-passive = <250>;
3861 polling-delay = <1000>;
3862
3863 thermal-sensors = <&tsens0 15>;
3864
3865 trips {
3866 trip-point0 {
3867 temperature = <90000>;

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4001 trip-point0 {
4002 temperature = <90000>;
4003 hysteresis = <2000>;
4004 type = "hot";
4005 };
4006 };
4007 };
4008
3909 polling-delay-passive = <250>;
3910 polling-delay = <1000>;
3911
3912 thermal-sensors = <&tsens0 15>;
3913
3914 trips {
3915 trip-point0 {
3916 temperature = <90000>;

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4050 trip-point0 {
4051 temperature = <90000>;
4052 hysteresis = <2000>;
4053 type = "hot";
4054 };
4055 };
4056 };
4057
4009 gpu-thermal-bottom {
4058 gpu-bottom-thermal {
4010 polling-delay-passive = <250>;
4011 polling-delay = <1000>;
4012
4013 thermal-sensors = <&tsens1 11>;
4014
4015 trips {
4016 trip-point0 {
4017 temperature = <90000>;

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4060 polling-delay = <1000>;
4061
4062 thermal-sensors = <&tsens1 11>;
4063
4064 trips {
4065 trip-point0 {
4066 temperature = <90000>;

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