ipq9574.dtsi (2e0580e10e919b544d7be1b2b8fc48fc7dff1322) ipq9574.dtsi (581dcbe60b6390c633f318a29db41d1df642e6d8)
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * IPQ9574 SoC device tree source
4 *
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
7 */
8

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616 reg = <0x0b128000 0x1000>;
617 frame-number = <6>;
618 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
619 status = "disabled";
620 };
621 };
622 };
623
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * IPQ9574 SoC device tree source
4 *
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
7 */
8

--- 607 unchanged lines hidden (view full) ---

616 reg = <0x0b128000 0x1000>;
617 frame-number = <6>;
618 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
619 status = "disabled";
620 };
621 };
622 };
623
624 thermal-zones {
625 nss-top-thermal {
626 polling-delay-passive = <0>;
627 polling-delay = <0>;
628 thermal-sensors = <&tsens 3>;
629
630 trips {
631 nss-top-critical {
632 temperature = <125000>;
633 hysteresis = <1000>;
634 type = "critical";
635 };
636 };
637 };
638
639 ubi-0-thermal {
640 polling-delay-passive = <0>;
641 polling-delay = <0>;
642 thermal-sensors = <&tsens 4>;
643
644 trips {
645 ubi_0-critical {
646 temperature = <125000>;
647 hysteresis = <1000>;
648 type = "critical";
649 };
650 };
651 };
652
653 ubi-1-thermal {
654 polling-delay-passive = <0>;
655 polling-delay = <0>;
656 thermal-sensors = <&tsens 5>;
657
658 trips {
659 ubi_1-critical {
660 temperature = <125000>;
661 hysteresis = <1000>;
662 type = "critical";
663 };
664 };
665 };
666
667 ubi-2-thermal {
668 polling-delay-passive = <0>;
669 polling-delay = <0>;
670 thermal-sensors = <&tsens 6>;
671
672 trips {
673 ubi_2-critical {
674 temperature = <125000>;
675 hysteresis = <1000>;
676 type = "critical";
677 };
678 };
679 };
680
681 ubi-3-thermal {
682 polling-delay-passive = <0>;
683 polling-delay = <0>;
684 thermal-sensors = <&tsens 7>;
685
686 trips {
687 ubi_3-critical {
688 temperature = <125000>;
689 hysteresis = <1000>;
690 type = "critical";
691 };
692 };
693 };
694
695 cpuss0-thermal {
696 polling-delay-passive = <0>;
697 polling-delay = <0>;
698 thermal-sensors = <&tsens 8>;
699
700 trips {
701 cpu-critical {
702 temperature = <125000>;
703 hysteresis = <1000>;
704 type = "critical";
705 };
706 };
707 };
708
709 cpuss1-thermal {
710 polling-delay-passive = <0>;
711 polling-delay = <0>;
712 thermal-sensors = <&tsens 9>;
713
714 trips {
715 cpu-critical {
716 temperature = <125000>;
717 hysteresis = <1000>;
718 type = "critical";
719 };
720 };
721 };
722
723 cpu0-thermal {
724 polling-delay-passive = <0>;
725 polling-delay = <0>;
726 thermal-sensors = <&tsens 10>;
727
728 trips {
729 cpu-critical {
730 temperature = <120000>;
731 hysteresis = <10000>;
732 type = "critical";
733 };
734
735 cpu-passive {
736 temperature = <110000>;
737 hysteresis = <1000>;
738 type = "passive";
739 };
740 };
741 };
742
743 cpu1-thermal {
744 polling-delay-passive = <0>;
745 polling-delay = <0>;
746 thermal-sensors = <&tsens 11>;
747
748 trips {
749 cpu-critical {
750 temperature = <120000>;
751 hysteresis = <10000>;
752 type = "critical";
753 };
754
755 cpu-passive {
756 temperature = <110000>;
757 hysteresis = <1000>;
758 type = "passive";
759 };
760 };
761 };
762
763 cpu2-thermal {
764 polling-delay-passive = <0>;
765 polling-delay = <0>;
766 thermal-sensors = <&tsens 12>;
767
768 trips {
769 cpu-critical {
770 temperature = <120000>;
771 hysteresis = <10000>;
772 type = "critical";
773 };
774
775 cpu-passive {
776 temperature = <110000>;
777 hysteresis = <1000>;
778 type = "passive";
779 };
780 };
781 };
782
783 cpu3-thermal {
784 polling-delay-passive = <0>;
785 polling-delay = <0>;
786 thermal-sensors = <&tsens 13>;
787
788 trips {
789 cpu-critical {
790 temperature = <120000>;
791 hysteresis = <10000>;
792 type = "critical";
793 };
794
795 cpu-passive {
796 temperature = <110000>;
797 hysteresis = <1000>;
798 type = "passive";
799 };
800 };
801 };
802
803 wcss-phyb-thermal {
804 polling-delay-passive = <0>;
805 polling-delay = <0>;
806 thermal-sensors = <&tsens 14>;
807
808 trips {
809 wcss_phyb-critical {
810 temperature = <125000>;
811 hysteresis = <1000>;
812 type = "critical";
813 };
814 };
815 };
816
817 top-glue-thermal {
818 polling-delay-passive = <0>;
819 polling-delay = <0>;
820 thermal-sensors = <&tsens 15>;
821
822 trips {
823 top_glue-critical {
824 temperature = <125000>;
825 hysteresis = <1000>;
826 type = "critical";
827 };
828 };
829 };
830 };
831
624 timer {
625 compatible = "arm,armv8-timer";
626 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
627 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
628 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
629 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
630 };
631};
832 timer {
833 compatible = "arm,armv8-timer";
834 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
835 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
836 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
837 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
838 };
839};