mt7622.dtsi (9a5a14948574ee09f339990cab69b4ab997d2f7d) mt7622.dtsi (837f0b9ae29ef45e1ecb5ec18bbac8c032a5989a)
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8

--- 269 unchanged lines hidden (view full) ---

278 #address-cells = <1>;
279 #size-cells = <1>;
280
281 thermal_calibration: calib@198 {
282 reg = <0x198 0xc>;
283 };
284 };
285
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8

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278 #address-cells = <1>;
279 #size-cells = <1>;
280
281 thermal_calibration: calib@198 {
282 reg = <0x198 0xc>;
283 };
284 };
285
286 apmixedsys: apmixedsys@10209000 {
287 compatible = "mediatek,mt7622-apmixedsys",
288 "syscon";
286 apmixedsys: clock-controller@10209000 {
287 compatible = "mediatek,mt7622-apmixedsys";
289 reg = <0 0x10209000 0 0x1000>;
290 #clock-cells = <1>;
291 };
292
288 reg = <0 0x10209000 0 0x1000>;
289 #clock-cells = <1>;
290 };
291
293 topckgen: topckgen@10210000 {
294 compatible = "mediatek,mt7622-topckgen",
295 "syscon";
292 topckgen: clock-controller@10210000 {
293 compatible = "mediatek,mt7622-topckgen";
296 reg = <0 0x10210000 0 0x1000>;
297 #clock-cells = <1>;
298 };
299
300 rng: rng@1020f000 {
301 compatible = "mediatek,mt7622-rng",
302 "mediatek,mt7623-rng";
303 reg = <0 0x1020f000 0 0x1000>;

--- 425 unchanged lines hidden (view full) ---

729 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
730
731 mediatek,infracfg = <&infracfg>;
732 status = "disabled";
733
734 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
735 };
736
294 reg = <0 0x10210000 0 0x1000>;
295 #clock-cells = <1>;
296 };
297
298 rng: rng@1020f000 {
299 compatible = "mediatek,mt7622-rng",
300 "mediatek,mt7623-rng";
301 reg = <0 0x1020f000 0 0x1000>;

--- 425 unchanged lines hidden (view full) ---

727 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
728
729 mediatek,infracfg = <&infracfg>;
730 status = "disabled";
731
732 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
733 };
734
737 ssusbsys: ssusbsys@1a000000 {
738 compatible = "mediatek,mt7622-ssusbsys",
739 "syscon";
735 ssusbsys: clock-controller@1a000000 {
736 compatible = "mediatek,mt7622-ssusbsys";
740 reg = <0 0x1a000000 0 0x1000>;
741 #clock-cells = <1>;
742 #reset-cells = <1>;
743 };
744
745 ssusb: usb@1a0c0000 {
746 compatible = "mediatek,mt7622-xhci",
747 "mediatek,mtk-xhci";

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788 u2port1: usb-phy@1a0c5000 {
789 reg = <0 0x1a0c5000 0 0x0100>;
790 #phy-cells = <1>;
791 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
792 clock-names = "ref";
793 };
794 };
795
737 reg = <0 0x1a000000 0 0x1000>;
738 #clock-cells = <1>;
739 #reset-cells = <1>;
740 };
741
742 ssusb: usb@1a0c0000 {
743 compatible = "mediatek,mt7622-xhci",
744 "mediatek,mtk-xhci";

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785 u2port1: usb-phy@1a0c5000 {
786 reg = <0 0x1a0c5000 0 0x0100>;
787 #phy-cells = <1>;
788 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
789 clock-names = "ref";
790 };
791 };
792
796 pciesys: pciesys@1a100800 {
797 compatible = "mediatek,mt7622-pciesys",
798 "syscon";
793 pciesys: clock-controller@1a100800 {
794 compatible = "mediatek,mt7622-pciesys";
799 reg = <0 0x1a100800 0 0x1000>;
800 #clock-cells = <1>;
801 #reset-cells = <1>;
802 };
803
804 pciecfg: pciecfg@1a140000 {
805 compatible = "mediatek,generic-pciecfg", "syscon";
806 reg = <0 0x1a140000 0 0x1000>;

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916 sata_port: sata-phy@1a243000 {
917 reg = <0 0x1a243000 0 0x0100>;
918 clocks = <&topckgen CLK_TOP_ETH_500M>;
919 clock-names = "ref";
920 #phy-cells = <1>;
921 };
922 };
923
795 reg = <0 0x1a100800 0 0x1000>;
796 #clock-cells = <1>;
797 #reset-cells = <1>;
798 };
799
800 pciecfg: pciecfg@1a140000 {
801 compatible = "mediatek,generic-pciecfg", "syscon";
802 reg = <0 0x1a140000 0 0x1000>;

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912 sata_port: sata-phy@1a243000 {
913 reg = <0 0x1a243000 0 0x0100>;
914 clocks = <&topckgen CLK_TOP_ETH_500M>;
915 clock-names = "ref";
916 #phy-cells = <1>;
917 };
918 };
919
924 hifsys: syscon@1af00000 {
925 compatible = "mediatek,mt7622-hifsys", "syscon";
920 hifsys: clock-controller@1af00000 {
921 compatible = "mediatek,mt7622-hifsys";
926 reg = <0 0x1af00000 0 0x70>;
922 reg = <0 0x1af00000 0 0x70>;
923 #clock-cells = <1>;
927 };
928
924 };
925
929 ethsys: syscon@1b000000 {
926 ethsys: clock-controller@1b000000 {
930 compatible = "mediatek,mt7622-ethsys",
931 "syscon";
932 reg = <0 0x1b000000 0 0x1000>;
933 #clock-cells = <1>;
934 #reset-cells = <1>;
935 };
936
937 hsdma: dma-controller@1b007000 {

--- 73 unchanged lines hidden --- 		927 compatible = "mediatek,mt7622-ethsys",
928 "syscon";
929 reg = <0 0x1b000000 0 0x1000>;
930 #clock-cells = <1>;
931 #reset-cells = <1>;
932 };
933
934 hsdma: dma-controller@1b007000 {

--- 73 unchanged lines hidden ---