mt7622.dtsi (80dd27b6c68c7189b865b4b966aa12c77d1adc1e) mt7622.dtsi (5ba090a03af2074841342bbe5fee45260ec62144)
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8

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547 <&pericfg CLK_PERI_SNFI_PD>;
548 clock-names = "nfi_clk", "pad_clk";
549 ecc-engine = <&bch>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 status = "disabled";
553 };
554
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8

--- 538 unchanged lines hidden (view full) ---

547 <&pericfg CLK_PERI_SNFI_PD>;
548 clock-names = "nfi_clk", "pad_clk";
549 ecc-engine = <&bch>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 status = "disabled";
553 };
554
555 snfi: spi@1100d000 {
556 compatible = "mediatek,mt7622-snand";
557 reg = <0 0x1100d000 0 0x1000>;
558 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
559 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
560 clock-names = "nfi_clk", "pad_clk";
561 nand-ecc-engine = <&bch>;
562 #address-cells = <1>;
563 #size-cells = <0>;
564 status = "disabled";
565 };
566
555 bch: ecc@1100e000 {
556 compatible = "mediatek,mt7622-ecc";
557 reg = <0 0x1100e000 0 0x1000>;
558 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
559 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
560 clock-names = "nfiecc_clk";
561 status = "disabled";
562 };

--- 405 unchanged lines hidden --- 		567 bch: ecc@1100e000 {
568 compatible = "mediatek,mt7622-ecc";
569 reg = <0 0x1100e000 0 0x1000>;
570 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
571 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
572 clock-names = "nfiecc_clk";
573 status = "disabled";
574 };

--- 405 unchanged lines hidden ---