mt7622.dtsi (5f599b3a0bb8e24300eac5654a74f2e2af256f04) mt7622.dtsi (26907b5354daab98b50c0bd9098c770a68369dc4)
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8

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537 pciesys: pciesys@1a100800 {
538 compatible = "mediatek,mt7622-pciesys",
539 "syscon";
540 reg = <0 0x1a100800 0 0x1000>;
541 #clock-cells = <1>;
542 #reset-cells = <1>;
543 };
544
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8

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537 pciesys: pciesys@1a100800 {
538 compatible = "mediatek,mt7622-pciesys",
539 "syscon";
540 reg = <0 0x1a100800 0 0x1000>;
541 #clock-cells = <1>;
542 #reset-cells = <1>;
543 };
544
545 pcie: pcie@1a140000 {
546 compatible = "mediatek,mt7622-pcie";
547 device_type = "pci";
548 reg = <0 0x1a140000 0 0x1000>,
549 <0 0x1a143000 0 0x1000>,
550 <0 0x1a145000 0 0x1000>;
551 reg-names = "subsys", "port0", "port1";
552 #address-cells = <3>;
553 #size-cells = <2>;
554 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
555 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
556 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
557 <&pciesys CLK_PCIE_P1_MAC_EN>,
558 <&pciesys CLK_PCIE_P0_AHB_EN>,
559 <&pciesys CLK_PCIE_P0_AHB_EN>,
560 <&pciesys CLK_PCIE_P0_AUX_EN>,
561 <&pciesys CLK_PCIE_P1_AUX_EN>,
562 <&pciesys CLK_PCIE_P0_AXI_EN>,
563 <&pciesys CLK_PCIE_P1_AXI_EN>,
564 <&pciesys CLK_PCIE_P0_OBFF_EN>,
565 <&pciesys CLK_PCIE_P1_OBFF_EN>,
566 <&pciesys CLK_PCIE_P0_PIPE_EN>,
567 <&pciesys CLK_PCIE_P1_PIPE_EN>;
568 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
569 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
570 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
571 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
572 bus-range = <0x00 0xff>;
573 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
574 status = "disabled";
575
576 pcie0: pcie@0,0 {
577 reg = <0x0000 0 0 0 0>;
578 #address-cells = <3>;
579 #size-cells = <2>;
580 #interrupt-cells = <1>;
581 ranges;
582 status = "disabled";
583
584 num-lanes = <1>;
585 interrupt-map-mask = <0 0 0 7>;
586 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
587 <0 0 0 2 &pcie_intc0 1>,
588 <0 0 0 3 &pcie_intc0 2>,
589 <0 0 0 4 &pcie_intc0 3>;
590 pcie_intc0: interrupt-controller {
591 interrupt-controller;
592 #address-cells = <0>;
593 #interrupt-cells = <1>;
594 };
595 };
596
597 pcie1: pcie@1,0 {
598 reg = <0x0800 0 0 0 0>;
599 #address-cells = <3>;
600 #size-cells = <2>;
601 #interrupt-cells = <1>;
602 ranges;
603 status = "disabled";
604
605 num-lanes = <1>;
606 interrupt-map-mask = <0 0 0 7>;
607 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
608 <0 0 0 2 &pcie_intc1 1>,
609 <0 0 0 3 &pcie_intc1 2>,
610 <0 0 0 4 &pcie_intc1 3>;
611 pcie_intc1: interrupt-controller {
612 interrupt-controller;
613 #address-cells = <0>;
614 #interrupt-cells = <1>;
615 };
616 };
617 };
618
545 ethsys: syscon@1b000000 {
546 compatible = "mediatek,mt7622-ethsys",
547 "syscon";
548 reg = <0 0x1b000000 0 0x1000>;
549 #clock-cells = <1>;
550 #reset-cells = <1>;
551 };
552

--- 38 unchanged lines hidden --- 		619 ethsys: syscon@1b000000 {
620 compatible = "mediatek,mt7622-ethsys",
621 "syscon";
622 reg = <0 0x1b000000 0 0x1000>;
623 #clock-cells = <1>;
624 #reset-cells = <1>;
625 };
626

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