hi6220.dtsi (f594d0b9b34aeb8e3ffa524eaa8a4085afb56d22) hi6220.dtsi (3814b61bd784cc7da966dc983a692035b7028776)
1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/hisi,hi6220-resets.h>

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257 };
258
259 pm_ctrl: pm_ctrl@f7032000 {
260 compatible = "hisilicon,hi6220-pmctrl", "syscon";
261 reg = <0x0 0xf7032000 0x0 0x1000>;
262 #clock-cells = <1>;
263 };
264
1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/hisi,hi6220-resets.h>

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257 };
258
259 pm_ctrl: pm_ctrl@f7032000 {
260 compatible = "hisilicon,hi6220-pmctrl", "syscon";
261 reg = <0x0 0xf7032000 0x0 0x1000>;
262 #clock-cells = <1>;
263 };
264
265 medianoc_ade: medianoc_ade@f4520000 {
266 compatible = "syscon";
267 reg = <0x0 0xf4520000 0x0 0x4000>;
268 };
269
265 stub_clock: stub_clock {
266 compatible = "hisilicon,hi6220-stub-clk";
267 hisilicon,hi6220-clk-sram = <&sram>;
268 #clock-cells = <1>;
269 mbox-names = "mbox-tx";
270 mboxes = <&mailbox 1 0 11>;
271 };
272

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845 cooling-maps {
846 map0 {
847 trip = <&target>;
848 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
849 };
850 };
851 };
852 };
270 stub_clock: stub_clock {
271 compatible = "hisilicon,hi6220-stub-clk";
272 hisilicon,hi6220-clk-sram = <&sram>;
273 #clock-cells = <1>;
274 mbox-names = "mbox-tx";
275 mboxes = <&mailbox 1 0 11>;
276 };
277

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850 cooling-maps {
851 map0 {
852 trip = <&target>;
853 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
854 };
855 };
856 };
857 };
858
859 ade: ade@f4100000 {
860 compatible = "hisilicon,hi6220-ade";
861 reg = <0x0 0xf4100000 0x0 0x7800>;
862 reg-names = "ade_base";
863 hisilicon,noc-syscon = <&medianoc_ade>;
864 resets = <&media_ctrl MEDIA_ADE>;
865 interrupts = <0 115 4>; /* ldi interrupt */
866
867 clocks = <&media_ctrl HI6220_ADE_CORE>,
868 <&media_ctrl HI6220_CODEC_JPEG>,
869 <&media_ctrl HI6220_ADE_PIX_SRC>;
870 /*clock name*/
871 clock-names = "clk_ade_core",
872 "clk_codec_jpeg",
873 "clk_ade_pix";
874
875 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
876 <&media_ctrl HI6220_CODEC_JPEG>;
877 assigned-clock-rates = <360000000>, <288000000>;
878 dma-coherent;
879 status = "disabled";
880
881 port {
882 ade_out: endpoint {
883 remote-endpoint = <&dsi_in>;
884 };
885 };
886 };
887
888 dsi: dsi@f4107800 {
889 compatible = "hisilicon,hi6220-dsi";
890 reg = <0x0 0xf4107800 0x0 0x100>;
891 clocks = <&media_ctrl HI6220_DSI_PCLK>;
892 clock-names = "pclk";
893 status = "disabled";
894
895 ports {
896 #address-cells = <1>;
897 #size-cells = <0>;
898
899 /* 0 for input port */
900 port@0 {
901 reg = <0>;
902 dsi_in: endpoint {
903 remote-endpoint = <&ade_out>;
904 };
905 };
906 };
907 };
853 };
854};
908 };
909};